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Message-ID: <a885301e-9105-83d1-13aa-8620b100d7a9@broadcom.com>
Date: Mon, 31 Oct 2022 11:05:59 -0700
From: William Zhang <william.zhang@...adcom.com>
To: Pierre Gondois <pierre.gondois@....com>,
linux-kernel@...r.kernel.org
Cc: Rob.Herring@....com, Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Anand Gore <anand.gore@...adcom.com>,
Kursad Oney <kursad.oney@...adcom.com>,
Florian Fainelli <f.fainelli@...il.com>,
Broadcom internal kernel review list
<bcm-kernel-feedback-list@...adcom.com>,
Ray Jui <rjui@...adcom.com>,
Scott Branden <sbranden@...adcom.com>,
Rafał Miłecki <rafal@...ecki.pl>,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH 05/20] arm64: dts: Update cache properties for broadcom
On 10/31/2022 02:19 AM, Pierre Gondois wrote:
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
>
> The recently added init_of_cache_level() function checks
> these properties. Add them if missing.
>
> Signed-off-by: Pierre Gondois <pierre.gondois@....com>
> ---
> arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi | 1 +
> arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi | 1 +
> arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi | 1 +
> arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi | 1 +
> arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi | 1 +
> arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi | 1 +
> arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi | 1 +
> arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi | 1 +
> arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi | 4 ++++
> 9 files changed, 12 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
> index 967d2cd3c3ce..5035a3cc90e0 100644
> --- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
> +++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
> @@ -63,6 +63,7 @@ cpu3: cpu@3 {
>
> l2: l2-cache0 {
> compatible = "cache";
> + cache-level = <2>;
> };
> };
>
> diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
> index 3d016c2ce675..d5bc31980f03 100644
> --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
> +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
> @@ -51,6 +51,7 @@ B53_3: cpu@3 {
>
> L2_0: l2-cache0 {
> compatible = "cache";
> + cache-level = <2>;
> };
> };
>
> diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
> index 04de96bd0a03..6f805266d3c9 100644
> --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
> +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
> @@ -35,6 +35,7 @@ B53_1: cpu@1 {
>
> L2_0: l2-cache0 {
> compatible = "cache";
> + cache-level = <2>;
> };
> };
>
> diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
> index 13629702f70b..b982249b80a2 100644
> --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
> +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
> @@ -51,6 +51,7 @@ B53_3: cpu@3 {
>
> L2_0: l2-cache0 {
> compatible = "cache";
> + cache-level = <2>;
> };
> };
>
> diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
> index c3e6197be808..a996d436e977 100644
> --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
> +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
> @@ -51,6 +51,7 @@ B53_3: cpu@3 {
>
> L2_0: l2-cache0 {
> compatible = "cache";
> + cache-level = <2>;
> };
> };
>
> diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
> index 0bce6497219f..62c530d4b103 100644
> --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
> +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
> @@ -35,6 +35,7 @@ B53_1: cpu@1 {
>
> L2_0: l2-cache0 {
> compatible = "cache";
> + cache-level = <2>;
> };
> };
>
> diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
> index 29a880c6c858..ba3d5a98ccbc 100644
> --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
> +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
> @@ -50,6 +50,7 @@ B53_3: cpu@3 {
> };
> L2_0: l2-cache0 {
> compatible = "cache";
> + cache-level = <2>;
> };
> };
>
> diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi
> index fda97c47f4e9..18cdbc20f03f 100644
> --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi
> +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi
> @@ -79,6 +79,7 @@ A57_3: cpu@3 {
>
> CLUSTER0_L2: l2-cache@0 {
> compatible = "cache";
> + cache-level = <2>;
> };
> };
>
> diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
> index 8f8c25e51194..e05901abe957 100644
> --- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
> +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
> @@ -108,18 +108,22 @@ cpu@301 {
>
> CLUSTER0_L2: l2-cache@0 {
> compatible = "cache";
> + cache-level = <2>;
> };
>
> CLUSTER1_L2: l2-cache@100 {
> compatible = "cache";
> + cache-level = <2>;
> };
>
> CLUSTER2_L2: l2-cache@200 {
> compatible = "cache";
> + cache-level = <2>;
> };
>
> CLUSTER3_L2: l2-cache@300 {
> compatible = "cache";
> + cache-level = <2>;
> };
> };
>
>
Acked-by: William Zhang <william.zhang@...adcom.com>
Thanks Pierre!
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