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Message-ID: <7d4f7f9e-a54c-c00e-2da7-c3e6dfd79869@intel.com>
Date:   Tue, 1 Nov 2022 19:14:45 +0200
From:   Adrian Hunter <adrian.hunter@...el.com>
To:     Victor Shih <victorshihgli@...il.com>, ulf.hansson@...aro.org
Cc:     linux-mmc@...r.kernel.org, linux-kernel@...r.kernel.org,
        benchuanggli@...il.com, HL.Liu@...esyslogic.com.tw,
        Greg.tu@...esyslogic.com.tw, takahiro.akashi@...aro.org,
        dlunev@...omium.org, Victor Shih <victor.shih@...esyslogic.com.tw>,
        Ben Chuang <ben.chuang@...esyslogic.com.tw>
Subject: Re: [PATCH V5 17/26] mmc: sdhci-uhs2: add clock operations

On 19/10/22 14:06, Victor Shih wrote:
> This is a sdhci version of mmc's uhs2_[enable|disable]_clk operations.
> 
> Signed-off-by: Ben Chuang <ben.chuang@...esyslogic.com.tw>
> Signed-off-by: AKASHI Takahiro <takahiro.akashi@...aro.org>
> Signed-off-by: Victor Shih <victor.shih@...esyslogic.com.tw>
> ---
>  drivers/mmc/host/sdhci-uhs2.c | 36 +++++++++++++++++++++++++++++++++++
>  1 file changed, 36 insertions(+)
> 
> diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c
> index 9ceae552c323..afaca5d96938 100644
> --- a/drivers/mmc/host/sdhci-uhs2.c
> +++ b/drivers/mmc/host/sdhci-uhs2.c
> @@ -11,6 +11,7 @@
>   */
>  
>  #include <linux/delay.h>
> +#include <linux/ktime.h>
>  #include <linux/module.h>
>  
>  #include "sdhci.h"
> @@ -403,6 +404,37 @@ int sdhci_uhs2_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
>  	return 0;
>  }
>  
> +static int sdhci_uhs2_disable_clk(struct mmc_host *mmc)
> +{
> +	struct sdhci_host *host = mmc_priv(mmc);
> +	u16 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
> +
> +	clk &= ~SDHCI_CLOCK_CARD_EN;
> +	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
> +
> +	return 0;
> +}
> +
> +static int sdhci_uhs2_enable_clk(struct mmc_host *mmc)
> +{
> +	struct sdhci_host *host = mmc_priv(mmc);
> +	u16 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
> +	u32 val;
> +	/* 20ms */
> +	int timeout_us = 20000;
> +
> +	clk |= SDHCI_CLOCK_CARD_EN;
> +	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
> +
> +	if (read_poll_timeout_atomic(sdhci_readw, val, (val & SDHCI_CLOCK_INT_STABLE),
> +				     10, timeout_us, true, host, SDHCI_CLOCK_CONTROL)) {
> +		pr_err("%s: Internal clock never stabilised.\n", mmc_hostname(host->mmc));
> +		sdhci_dumpregs(host);
> +		return 1;
> +	}
> +	return 0;
> +}
> +
>  /*****************************************************************************\
>   *                                                                           *
>   * Driver init/exit                                                          *
> @@ -560,6 +592,10 @@ static int sdhci_uhs2_host_ops_init(struct sdhci_host *host)
>  
>  	if (!host->mmc_host_ops.uhs2_detect_init)
>  		host->mmc_host_ops.uhs2_detect_init = sdhci_uhs2_do_detect_init;
> +	if (!host->mmc_host_ops.uhs2_disable_clk)
> +		host->mmc_host_ops.uhs2_disable_clk = sdhci_uhs2_disable_clk;
> +	if (!host->mmc_host_ops.uhs2_enable_clk)
> +		host->mmc_host_ops.uhs2_enable_clk = sdhci_uhs2_enable_clk;

As mentioned before ->uhs2_disable_clk() and ->uhs2_enable_clk()
are never called.

>  
>  	return 0;
>  }

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