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Message-Id: <20221102173843.409039-1-dinguyen@kernel.org>
Date: Wed, 2 Nov 2022 12:38:38 -0500
From: Dinh Nguyen <dinguyen@...nel.org>
To: jh80.chung@...sung.com
Cc: dinguyen@...nel.org, ulf.hansson@...aro.org, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, mturquette@...libre.com,
sboyd@...nel.org, linux-mmc@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-clk@...r.kernel.org
Subject: [PATCHv7 1/6] dt-bindings: mmc: synopsys-dw-mshc: document "altr,sysmgr-syscon"
Document the optional "altr,sysmgr-syscon" binding that is used to
access the System Manager register that controls the SDMMC clock
phase.
Signed-off-by: Dinh Nguyen <dinguyen@...nel.org>
---
v7: and "not" for the required "altr,sysmgr-syscon" binding
v6: make "altr,sysmgr-syscon" optional
v5: document reg shift
v4: add else statement
v3: document that the "altr,sysmgr-syscon" binding is only applicable to
"altr,socfpga-dw-mshc"
v2: document "altr,sysmgr-syscon" in the MMC section
---
.../bindings/mmc/synopsys-dw-mshc.yaml | 33 +++++++++++++++++--
1 file changed, 30 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml
index ae6d6fca79e2..80dd3d72424f 100644
--- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml
+++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml
@@ -6,9 +6,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Synopsys Designware Mobile Storage Host Controller Binding
-allOf:
- - $ref: "synopsys-dw-mshc-common.yaml#"
-
maintainers:
- Ulf Hansson <ulf.hansson@...aro.org>
@@ -38,6 +35,36 @@ properties:
- const: biu
- const: ciu
+ altr,sysmgr-syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle to the sysmgr node
+ - description: register offset that controls the SDMMC clock phase
+ - description: register shift for the smplsel(drive in) setting
+ description:
+ This property is optional. Contains the phandle to System Manager block
+ that contains the SDMMC clock-phase control register. The first value is
+ the pointer to the sysmgr, the 2nd value is the register offset for the
+ SDMMC clock phase register, and the 3rd value is the bit shift for the
+ smplsel(drive in) setting.
+
+allOf:
+ - $ref: "synopsys-dw-mshc-common.yaml#"
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: altr,socfpga-dw-mshc
+ then:
+ not:
+ required:
+ - altr,sysmgr-syscon
+ else:
+ properties:
+ altr,sysmgr-syscon: false
+
required:
- compatible
- reg
--
2.25.1
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