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Message-ID: <c00a4715-94f7-2d4a-02b3-533bb309c130@intel.com>
Date:   Wed, 2 Nov 2022 11:21:52 -0700
From:   Dave Hansen <dave.hansen@...el.com>
To:     Paolo Bonzini <pbonzini@...hat.com>,
        Jiaxi Chen <jiaxi.chen@...ux.intel.com>, kvm@...r.kernel.org
Cc:     tglx@...utronix.de, mingo@...hat.com, bp@...en8.de,
        dave.hansen@...ux.intel.com, x86@...nel.org, hpa@...or.com,
        seanjc@...gle.com, ndesaulniers@...gle.com,
        alexandre.belloni@...tlin.com, peterz@...radead.org,
        jpoimboe@...nel.org, chang.seok.bae@...el.com,
        pawan.kumar.gupta@...ux.intel.com, babu.moger@....com,
        jmattson@...gle.com, sandipan.das@....com, tony.luck@...el.com,
        sathyanarayanan.kuppuswamy@...ux.intel.com, fenghua.yu@...el.com,
        keescook@...omium.org, jane.malalane@...rix.com, nathan@...nel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH 2/6] x86: KVM: Enable AMX-FP16 CPUID and expose it to
 guest

On 11/2/22 11:16, Paolo Bonzini wrote:
> On 11/2/22 19:14, Dave Hansen wrote:
>>>         kvm_cpu_cap_mask(CPUID_7_1_EAX,
>>> -        F(AVX_VNNI) | F(AVX512_BF16) | F(CMPCCXADD)
>>> +        F(AVX_VNNI) | F(AVX512_BF16) | F(CMPCCXADD) | F(AMX_FP16)
>>>       );
>>>         kvm_cpu_cap_mask(CPUID_D_1_EAX,
>>
>> KVM folks, is the idea that every feature that is enumerated to a guest
>> needs to be in one of these masks?  Or is there something special about
>> the features in these masks?
> 
> Yes, all features are vetted manually to see whether they require new
> MSRs and the like.  Therefore, anything that userspace can set in the
> guest's CPUID must be in the list.

Makes sense.

Intel folks, when you add these bits, can you please include information
about the "vetting" that you performed?

For example, it would be handy to say:

	AMX_FP16 is just a new instruction that operates on existing AMX
	tile registers.  It needs no additional enabling on top of the
	existing kernel AMX enabling.

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