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Message-ID: <50209486-8f86-c84c-8493-c48a6b57e6c6@linaro.org>
Date: Wed, 2 Nov 2022 16:03:07 -0400
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Adam Skladowski <a39.skl@...il.com>
Cc: phone-devel@...r.kernel.org, ~postmarketos/upstreaming@...ts.sr.ht,
Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...ainline.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 1/1] arm64: dts: qcom: Add MSM8976 device tree
On 01/11/2022 15:16, Adam Skladowski wrote:
> Add a base DT for MSM8976 SoC.
>
> Signed-off-by: Adam Skladowski <a39.skl@...il.com>
> ---
> arch/arm64/boot/dts/qcom/msm8976.dtsi | 1310 +++++++++++++++++++++++++
> 1 file changed, 1310 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/msm8976.dtsi
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi
> new file mode 100644
> index 0000000000000..c073f16faa7ee
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi
> @@ -0,0 +1,1310 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/* Copyright (c) 2022, The Linux Foundation. All rights reserved. */
> +
> +#include <dt-bindings/clock/qcom,gcc-msm8976.h>
> +#include <dt-bindings/clock/qcom,rpmcc.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/power/qcom-rpmpd.h>
> +#include <dt-bindings/thermal/thermal.h>
> +
> +/ {
> + interrupt-parent = <&intc>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + chosen { };
> +
> + clocks {
> + xo_board_clk: xo_board_clk {
No underscores in node names.
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <19200000>;
> + };
> +
> + sleep_clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <32768>;
> + };
> + };
> +
(...)
> +
> + tcsr_mutex: hwlock@...5000 {
> + compatible = "qcom,tcsr-mutex";
> + reg = <0x01905000 0x20000>;
> + #hwlock-cells = <1>;
> + };
> +
> + tcsr: syscon@...7000 {
> + compatible = "qcom,tcsr-msm8976", "syscon";
Where is the documentation?
> + reg = <0x01937000 0x30000>;
> + };
> +
> + mdss: mdss@...0000 {
> + compatible = "qcom,mdss";
> +
> + reg = <0x01a00000 0x1000>,
> + <0x01ab0000 0x1040>;
> + reg-names = "mdss_phys",
> + "vbif_phys";
> +
> + power-domains = <&gcc MDSS_GDSC>;
> + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
> +
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + clocks = <&gcc GCC_MDSS_AHB_CLK>,
> + <&gcc GCC_MDSS_AXI_CLK>,
> + <&gcc GCC_MDSS_VSYNC_CLK>,
> + <&gcc GCC_MDSS_MDP_CLK>;
> + clock-names = "iface",
> + "bus",
> + "vsync",
> + "core";
> +
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + status = "disabled";
> +
> + mdp: mdp@...1000 {
I think other DTSes use different node name...
> + compatible = "qcom,mdp5";
> + reg = <0x01a01000 0x89000>;
> + reg-names = "mdp_phys";
> +
> + interrupt-parent = <&mdss>;
> + interrupts = <0>;
> +
> + power-domains = <&gcc MDSS_GDSC>;
> +
> + clocks = <&gcc GCC_MDSS_AHB_CLK>,
> + <&gcc GCC_MDSS_AXI_CLK>,
> + <&gcc GCC_MDSS_MDP_CLK>,
> + <&gcc GCC_MDSS_VSYNC_CLK>,
> + <&gcc GCC_MDP_TBU_CLK>,
> + <&gcc GCC_MDP_RT_TBU_CLK>;
> + clock-names = "iface",
> + "bus",
> + "core",
> + "vsync",
> + "tbu",
> + "tbu_rt";
> + iommus = <&apps_iommu 0x17>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + mdp5_intf1_out: endpoint {
> + remote-endpoint = <&dsi0_in>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + mdp5_intf2_out: endpoint {
> + remote-endpoint = <&dsi1_in>;
> + };
> + };
> + };
> + };
> +
> + dsi0: dsi@...4000 {
> + compatible = "qcom,mdss-dsi-ctrl";
> + reg = <0x01a94000 0x2d4>;
> + reg-names = "dsi_ctrl";
> +
> + interrupt-parent = <&mdss>;
> + interrupts = <4>;
> +
> + assigned-clocks = <&gcc GCC_MDSS_BYTE0_CLK_SRC>,
> + <&gcc GCC_MDSS_PCLK0_CLK_SRC>;
> + assigned-clock-parents = <&dsi0_phy 0>,
> + <&dsi0_phy 1>;
> +
> + clocks = <&gcc GCC_MDSS_MDP_CLK>,
> + <&gcc GCC_MDSS_AHB_CLK>,
> + <&gcc GCC_MDSS_AXI_CLK>,
> + <&gcc GCC_MDSS_BYTE0_CLK>,
> + <&gcc GCC_MDSS_PCLK0_CLK>,
> + <&gcc GCC_MDSS_ESC0_CLK>;
> + clock-names = "mdp_core",
> + "iface",
> + "bus",
> + "byte",
> + "pixel",
> + "core";
> +
> + phys = <&dsi0_phy>;
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dsi0_in: endpoint {
> + remote-endpoint = <&mdp5_intf1_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + dsi0_out: endpoint {
> + };
> + };
> + };
> + };
> +
> + dsi0_phy: phy@...4400 {
> + compatible = "qcom,dsi-phy-28nm-hpm-fam-b";
> + reg = <0x01a94400 0x20c>,
> + <0x01a94b80 0x2c>,
> + <0x01a94a00 0xd4>;
> + reg-names = "dsi_phy",
> + "dsi_phy_regulator",
> + "dsi_pll";
> +
> + #clock-cells = <1>;
> + #phy-cells = <0>;
> +
> + clocks = <&gcc GCC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
> + clock-names = "iface", "ref";
> +
> + status = "disabled";
> + };
> +
> + dsi1: dsi@...6000 {
> + compatible = "qcom,mdss-dsi-ctrl";
> + reg = <0x01a96000 0x2d4>;
> + reg-names = "dsi_ctrl";
> +
> + interrupt-parent = <&mdss>;
> + interrupts = <5>;
> +
> + assigned-clocks = <&gcc GCC_MDSS_BYTE1_CLK_SRC>,
> + <&gcc GCC_MDSS_PCLK1_CLK_SRC>;
> + assigned-clock-parents = <&dsi1_phy 0>,
> + <&dsi1_phy 1>;
> +
> + clocks = <&gcc GCC_MDSS_MDP_CLK>,
> + <&gcc GCC_MDSS_AHB_CLK>,
> + <&gcc GCC_MDSS_AXI_CLK>,
> + <&gcc GCC_MDSS_BYTE1_CLK>,
> + <&gcc GCC_MDSS_PCLK1_CLK>,
> + <&gcc GCC_MDSS_ESC1_CLK>;
> + clock-names = "mdp_core",
> + "iface",
> + "bus",
> + "byte",
> + "pixel",
> + "core";
> +
> + phys = <&dsi1_phy>;
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dsi1_in: endpoint {
> + remote-endpoint = <&mdp5_intf2_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + dsi1_out: endpoint {
> + };
> + };
> + };
> + };
> +
> + dsi1_phy: phy@...6400 {
> + compatible = "qcom,dsi-phy-28nm-hpm-fam-b";
> + reg = <0x01a96400 0x20c>,
> + <0x01a96b80 0x2c>,
> + <0x01a96a00 0xd4>;
> + reg-names = "dsi_phy",
> + "dsi_phy_regulator",
> + "dsi_pll";
> +
> + #clock-cells = <1>;
> + #phy-cells = <0>;
> +
> + clocks = <&gcc GCC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
> + clock-names = "iface", "ref";
> +
> + status = "disabled";
> + };
> + };
> +
> + apps_iommu: iommu@...0000 {
> + compatible = "qcom,msm-iommu-v1";
> + ranges = <0 0x01e20000 0x20000>;
> +
> + clocks = <&gcc GCC_SMMU_CFG_CLK>,
> + <&gcc GCC_APSS_TCU_CLK>;
> + clock-names = "iface", "bus";
> +
> + qcom,iommu-secure-id = <17>;
> +
> + #address-cells = <1>;
> + #iommu-cells = <1>;
> + #size-cells = <1>;
> +
> + /* MDP_0 */
> + iommu-ctx@...00 {
> + compatible = "qcom,msm-iommu-v1-ns";
> + reg = <0x17000 0x1000>;
> + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + spmi_bus: spmi@...f000 {
> + compatible = "qcom,spmi-pmic-arb";
> + reg = <0x0200f000 0x1000>,
> + <0x02400000 0x800000>,
> + <0x02c00000 0x800000>,
> + <0x03800000 0x200000>,
> + <0x0200a000 0x2100>;
> + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
> + interrupt-names = "periph_irq";
> + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
> + qcom,ee = <0>;
> + qcom,channel = <0>;
> + interrupt-controller;
> +
> + #interrupt-cells = <4>;
> + #address-cells = <2>;
> + #size-cells = <0>;
> + };
> +
> + sdhc_1: mmc@...4900 {
> + compatible = "qcom,sdhci-msm-v4";
> +
> + reg = <0x07824900 0x500>, <0x07824000 0x800>;
> + reg-names = "hc", "core";
> +
> + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hc_irq", "pwr_irq";
> +
> + clocks = <&gcc GCC_SDCC1_AHB_CLK>,
> + <&gcc GCC_SDCC1_APPS_CLK>,
> + <&rpmcc RPM_SMD_XO_CLK_SRC>;
> + clock-names = "iface", "core", "xo";
> +
> + power-domains = <&rpmpd MSM8976_VDDCX>;
> + operating-points-v2 = <&sdhc1_opp_table>;
> +
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
> + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
> +
> + mmc-hs400-1_8v;
> + mmc-hs200-1_8v;
> + mmc-ddr-1_8v;
> + bus-width = <8>;
> + non-removable;
> +
> + status = "disabled";
> +
> + sdhc1_opp_table: opp-table-sdhc1 {
Did you test the DTS with dtbs_check?
Best regards,
Krzysztof
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