[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <060ad3b1-8a44-60d0-29d2-bdec6fd939c6@linaro.org>
Date: Wed, 2 Nov 2022 16:47:34 -0400
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Pierre Gondois <pierre.gondois@....com>,
linux-kernel@...r.kernel.org
Cc: Rob.Herring@....com, Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Andrew Lunn <andrew@...n.ch>,
Gregory Clement <gregory.clement@...tlin.com>,
Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>,
Vadym Kochan <vadym.kochan@...ision.eu>,
Chris Packham <chris.packham@...iedtelesis.co.nz>,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH 10/20] arm64: dts: Update cache properties for marvell
On 31/10/2022 05:20, Pierre Gondois wrote:
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
>
> The recently added init_of_cache_level() function checks
> these properties. Add them if missing.
>
> Signed-off-by: Pierre Gondois <pierre.gondois@....com>
Your threading is broken.
Best regards,
Krzysztof
Powered by blists - more mailing lists