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Message-ID: <Y2IuCFtbiw4H+T0C@hovoldconsulting.com>
Date: Wed, 2 Nov 2022 09:44:56 +0100
From: Johan Hovold <johan@...nel.org>
To: Manivannan Sadhasivam <mani@...nel.org>
Cc: Johan Hovold <johan+linaro@...nel.org>,
Stanimir Varbanov <svarbanov@...sol.com>,
Lorenzo Pieralisi <lpieralisi@...nel.org>,
Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...ainline.org>,
Bjorn Helgaas <bhelgaas@...gle.com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Krzysztof WilczyĆski <kw@...ux.com>,
Krishna chaitanya chundru <quic_krichai@...cinc.com>,
quic_vbadigan@...cinc.com, Brian Masney <bmasney@...hat.com>,
linux-arm-msm@...r.kernel.org, linux-pci@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 2/2] PCI: qcom: Add basic interconnect support
On Wed, Nov 02, 2022 at 09:38:31AM +0100, Johan Hovold wrote:
> On Tue, Nov 01, 2022 at 08:05:29PM +0530, Manivannan Sadhasivam wrote:
> > On Fri, Oct 21, 2022 at 08:46:16AM +0200, Johan Hovold wrote:
> > > On Qualcomm platforms like SC8280XP and SA8540P, interconnect bandwidth
> > > must be requested before enabling interconnect clocks.
> > >
> > > Add basic support for managing an optional "pcie-mem" interconnect path
> > > by setting a low constraint before enabling clocks and updating it after
> > > the link is up.
> > >
> > > Note that it is not possible for a controller driver to set anything but
> > > a maximum peak bandwidth as expected average bandwidth will vary with
> > > use case and actual use (and power policy?). This very much remains an
> > > unresolved problem with the interconnect framework.
> > >
> > > Also note that no constraint is set for the SC8280XP/SA8540P "cpu-pcie"
> > > path for now as it is not clear what an appropriate constraint would be
> > > (and the system does not crash when left unspecified).
> > > + }
> > > +
> > > + /*
> > > + * Some Qualcomm platforms require interconnect bandwidth constraints
> > > + * to be set before enabling interconnect clocks.
> > > + *
> > > + * Set an initial peak bandwidth corresponding to single-lane Gen 1
> > > + * for the pcie-mem path.
> > > + */
> > > + ret = icc_set_bw(pcie->icc_mem, 0, MBps_to_icc(250));
> > > + if (ret) {
> > > + dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",
> > > + ret);
> >
> > Move "ret);" to prior line. No need to keep up within 80 columns.
>
> 80 chars is still a soft limit and in this case there's no real gain in
> terms of readability from breaking it.
>
> But sure, I can remove the line break.
After looking at the result, I changed my mind here and will stick to
the 80 char limit.
Johan
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