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Message-ID: <166738035851.7716.7987336244095815440.tip-bot2@tip-bot2>
Date: Wed, 02 Nov 2022 09:12:38 -0000
From: "tip-bot2 for Peter Zijlstra" <tip-bot2@...utronix.de>
To: linux-tip-commits@...r.kernel.org
Cc: "Peter Zijlstra (Intel)" <peterz@...radead.org>, x86@...nel.org,
linux-kernel@...r.kernel.org
Subject: [tip: x86/mm] x86/mm/pae: Don't (ab)use atomic64
The following commit has been merged into the x86/mm branch of tip:
Commit-ID: a677802d5b0258f93f54620e1cd181b56547c36c
Gitweb: https://git.kernel.org/tip/a677802d5b0258f93f54620e1cd181b56547c36c
Author: Peter Zijlstra <peterz@...radead.org>
AuthorDate: Thu, 26 Nov 2020 17:38:42 +01:00
Committer: Peter Zijlstra <peterz@...radead.org>
CommitterDate: Tue, 01 Nov 2022 13:44:03 +01:00
x86/mm/pae: Don't (ab)use atomic64
PAE implies CX8, write readable code.
Signed-off-by: Peter Zijlstra (Intel) <peterz@...radead.org>
Link: https://lkml.kernel.org/r/20221022114424.971450128%40infradead.org
---
arch/x86/include/asm/pgtable-3level.h | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/arch/x86/include/asm/pgtable-3level.h b/arch/x86/include/asm/pgtable-3level.h
index 94f50b0..0a1b81d 100644
--- a/arch/x86/include/asm/pgtable-3level.h
+++ b/arch/x86/include/asm/pgtable-3level.h
@@ -2,8 +2,6 @@
#ifndef _ASM_X86_PGTABLE_3LEVEL_H
#define _ASM_X86_PGTABLE_3LEVEL_H
-#include <asm/atomic64_32.h>
-
/*
* Intel Physical Address Extension (PAE) Mode - three-level page
* tables on PPro+ CPUs.
@@ -95,11 +93,12 @@ static inline void pud_clear(pud_t *pudp)
#ifdef CONFIG_SMP
static inline pte_t native_ptep_get_and_clear(pte_t *ptep)
{
- pte_t res;
+ pte_t old = *ptep;
- res.pte = (pteval_t)arch_atomic64_xchg((atomic64_t *)ptep, 0);
+ do {
+ } while (!try_cmpxchg64(&ptep->pte, &old.pte, 0ULL));
- return res;
+ return old;
}
#else
#define native_ptep_get_and_clear(xp) native_local_ptep_get_and_clear(xp)
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