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Message-ID: <166738036632.7716.16970239696245313783.tip-bot2@tip-bot2>
Date: Wed, 02 Nov 2022 09:12:46 -0000
From: "tip-bot2 for Peter Zijlstra" <tip-bot2@...utronix.de>
To: linux-tip-commits@...r.kernel.org
Cc: Matthew Wilcox <willy@...radead.org>,
"Peter Zijlstra (Intel)" <peterz@...radead.org>, x86@...nel.org,
linux-kernel@...r.kernel.org
Subject: [tip: x86/mm] mm: Update ptep_get_lockless()'s comment
The following commit has been merged into the x86/mm branch of tip:
Commit-ID: 88993b1627f2a2205b2f3112c4d22448cd863df3
Gitweb: https://git.kernel.org/tip/88993b1627f2a2205b2f3112c4d22448cd863df3
Author: Peter Zijlstra <peterz@...radead.org>
AuthorDate: Thu, 26 Nov 2020 14:04:46 +01:00
Committer: Peter Zijlstra <peterz@...radead.org>
CommitterDate: Tue, 01 Nov 2022 13:43:59 +01:00
mm: Update ptep_get_lockless()'s comment
Improve the comment.
Suggested-by: Matthew Wilcox <willy@...radead.org>
Signed-off-by: Peter Zijlstra (Intel) <peterz@...radead.org>
Link: https://lkml.kernel.org/r/20221022114424.515572025%40infradead.org
---
include/linux/pgtable.h | 15 ++++++---------
1 file changed, 6 insertions(+), 9 deletions(-)
diff --git a/include/linux/pgtable.h b/include/linux/pgtable.h
index a108b60..c0b2900 100644
--- a/include/linux/pgtable.h
+++ b/include/linux/pgtable.h
@@ -300,15 +300,12 @@ static inline pte_t ptep_get(pte_t *ptep)
#ifdef CONFIG_GUP_GET_PTE_LOW_HIGH
/*
- * WARNING: only to be used in the get_user_pages_fast() implementation.
- *
- * With get_user_pages_fast(), we walk down the pagetables without taking any
- * locks. For this we would like to load the pointers atomically, but sometimes
- * that is not possible (e.g. without expensive cmpxchg8b on x86_32 PAE). What
- * we do have is the guarantee that a PTE will only either go from not present
- * to present, or present to not present or both -- it will not switch to a
- * completely different present page without a TLB flush in between; something
- * that we are blocking by holding interrupts off.
+ * For walking the pagetables without holding any locks. Some architectures
+ * (eg x86-32 PAE) cannot load the entries atomically without using expensive
+ * instructions. We are guaranteed that a PTE will only either go from not
+ * present to present, or present to not present -- it will not switch to a
+ * completely different present page without a TLB flush inbetween; which we
+ * are blocking by holding interrupts off.
*
* Setting ptes from not present to present goes:
*
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