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Message-ID: <9f2a50db-0cfe-b9ce-11f4-be406cb9888e@linaro.org>
Date: Wed, 2 Nov 2022 11:22:59 -0400
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Thippeswamy Havalige <thippeswamy.havalige@....com>,
linux-pci@...r.kernel.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org
Cc: bhelgaas@...gle.com, michals@...inx.com, robh+dt@...nel.org,
nagaradhesh.yeleswarapu@....com, bharat.kumar.gogada@....com
Subject: Re: [PATCH v2 2/2] dt-bindings: PCI: xilinx-nwl: Convert to YAML
schemas of Xilinx NWL PCIe Root Port Bridge
On 01/11/2022 01:20, Thippeswamy Havalige wrote:
> Convert to YAML schemas for Xilinx NWL PCIe Root Port Bridge
> dt binding.
>
> Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@....com>
> ---
> .../bindings/pci/xilinx-nwl-pcie.txt | 73 ----------
> .../bindings/pci/xlnx,nwl-pcie.yaml | 137 ++++++++++++++++++
> 2 files changed, 137 insertions(+), 73 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
> create mode 100644 Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
>
> diff --git a/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt b/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
> deleted file mode 100644
> index f56f8c58c5d9..000000000000
> --- a/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
> +++ /dev/null
> @@ -1,73 +0,0 @@
> -* Xilinx NWL PCIe Root Port Bridge DT description
> -
> -Required properties:
> -- compatible: Should contain "xlnx,nwl-pcie-2.11"
> -- #address-cells: Address representation for root ports, set to <3>
> -- #size-cells: Size representation for root ports, set to <2>
> -- #interrupt-cells: specifies the number of cells needed to encode an
> - interrupt source. The value must be 1.
> -- reg: Should contain Bridge, PCIe Controller registers location,
> - configuration space, and length
> -- reg-names: Must include the following entries:
> - "breg": bridge registers
> - "pcireg": PCIe controller registers
> - "cfg": configuration space region
> -- device_type: must be "pci"
> -- interrupts: Should contain NWL PCIe interrupt
> -- interrupt-names: Must include the following entries:
> - "msi1, msi0": interrupt asserted when an MSI is received
> - "intx": interrupt asserted when a legacy interrupt is received
> - "misc": interrupt asserted when miscellaneous interrupt is received
> -- interrupt-map-mask and interrupt-map: standard PCI properties to define the
> - mapping of the PCI interface to interrupt numbers.
> -- ranges: ranges for the PCI memory regions (I/O space region is not
> - supported by hardware)
> - Please refer to the standard PCI bus binding document for a more
> - detailed explanation
> -- msi-controller: indicates that this is MSI controller node
> -- msi-parent: MSI parent of the root complex itself
> -- legacy-interrupt-controller: Interrupt controller device node for Legacy
> - interrupts
> - - interrupt-controller: identifies the node as an interrupt controller
> - - #interrupt-cells: should be set to 1
> - - #address-cells: specifies the number of cells needed to encode an
> - address. The value must be 0.
> -
> -Optional properties:
> -- dma-coherent: present if DMA operations are coherent
> -- clocks: Input clock specifier. Refer to common clock bindings
> -
> -Example:
> -++++++++
> -
> -nwl_pcie: pcie@...e0000 {
> - #address-cells = <3>;
> - #size-cells = <2>;
> - compatible = "xlnx,nwl-pcie-2.11";
> - #interrupt-cells = <1>;
> - msi-controller;
> - device_type = "pci";
> - interrupt-parent = <&gic>;
> - interrupts = <0 114 4>, <0 115 4>, <0 116 4>, <0 117 4>, <0 118 4>;
> - interrupt-names = "msi0", "msi1", "intx", "dummy", "misc";
> - interrupt-map-mask = <0x0 0x0 0x0 0x7>;
> - interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
> - <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
> - <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
> - <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
> -
> - msi-parent = <&nwl_pcie>;
> - reg = <0x0 0xfd0e0000 0x0 0x1000>,
> - <0x0 0xfd480000 0x0 0x1000>,
> - <0x80 0x00000000 0x0 0x1000000>;
> - reg-names = "breg", "pcireg", "cfg";
> - ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */
> - 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
> -
> - pcie_intc: legacy-interrupt-controller {
> - interrupt-controller;
> - #address-cells = <0>;
> - #interrupt-cells = <1>;
> - };
> -
> -};
> diff --git a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
> new file mode 100644
> index 000000000000..f6634be618a2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
> @@ -0,0 +1,137 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/xlnx,nwl-pcie.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Xilinx NWL PCIe Root Port Bridge
> +
> +maintainers:
> + - Thippeswamy Havalige <thippeswamy.havalige@....com>
> +
> +allOf:
> + - $ref: /schemas/pci/pci-bus.yaml#
> + - $ref: /schemas/interrupt-controller/msi-controller.yaml#
> +
> +properties:
> + compatible:
> + const: xlnx,nwl-pcie-2.11
> +
> + reg:
> + items:
> + - description: PCIe bridge registers location.
> + - description: PCIe Controller registers location.
> + - description: PCIe Configuration space region.
> +
> + reg-names:
> + items:
> + - const: breg
const: bridge
> + - const: pcireg
const: pci
> + - const: cfg
> +
> + interrupts:
> + items:
> + - description: msi0 interrupt asserted when an MSI is received
> + - description: msi1 interrupt asserted when an MSI is received
> + - description: interrupt asserted when a legacy interrupt is received
> + - description: unused interrupt(dummy)
> + - description: interrupt asserted when miscellaneous interrupt is received
> +
> + interrupt-names:
> + maxItems: 5
I didn't notice last time - what are the names? They need to be defined.
> +
> + interrupt-map-mask:
> + items:
> + - const: 0
> + - const: 0
> + - const: 0
> + - const: 7
> +
Best regards,
Krzysztof
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