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Message-ID: <CAJZ5v0h=1UuPLPo1cS6zr+AFhYE-7F9YN-t+p8dgkOFs1EQ+SQ@mail.gmail.com>
Date: Thu, 3 Nov 2022 19:23:06 +0100
From: "Rafael J. Wysocki" <rafael@...nel.org>
To: Srinivas Pandruvada <srinivas.pandruvada@...ux.intel.com>
Cc: rafael@...nel.org, lenb@...nel.org, viresh.kumar@...aro.org,
linux-pm@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] cpufreq: intel_pstate: Allow EPP 0x80 setting by the firmware
On Thu, Oct 27, 2022 at 7:19 PM Srinivas Pandruvada
<srinivas.pandruvada@...ux.intel.com> wrote:
>
> With the
> "commit 3d13058ed2a6 ("cpufreq: intel_pstate: Use firmware default EPP")"
> the firmware can set an EPP, which driver will not overwrite. But the
> driver has a valid range check for:
> 0x40 > firmware epp < 0x80.
> Hence firmware can't specify EPP of 0x80.
>
> If the firmware didn't specify in the valid range, the driver has a
> hard coded EPP of 102. But some Chrome hardware vendors don't want
> this overwrite and wants to boot with chipset default EPP of 0x80 as
> this improves battery life.
>
> In this case they want to have capability to specify EPP of 0x80 via
> the firmware. This require the valid range to include 0x80 also.
> But here the valid range can't be simply extended to include 0x80 as
> this is the chipset default EPP. Even without any firmware specifying
> EPP, the chipset will always boot with EPP of 0x80.
>
> To make sure that firmware specified EPP of 0x80 and not by the
> chipset default, it will require additional check to make sure HWP
> was enabled by the firmware before boot. Only way the firmware can
> update EPP, is to enable HWP and update EPP via MSR_HWP_REQUEST.
>
> This driver already checks, if the HWP is enabled by the firmware.
> Use the same flag and extend valid range to include 0x80.
>
> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@...ux.intel.com>
> ---
> drivers/cpufreq/intel_pstate.c | 9 +++++----
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c
> index fc3ebeb0bbe5..c41875abd8be 100644
> --- a/drivers/cpufreq/intel_pstate.c
> +++ b/drivers/cpufreq/intel_pstate.c
> @@ -297,6 +297,7 @@ static int hwp_active __read_mostly;
> static int hwp_mode_bdw __read_mostly;
> static bool per_cpu_limits __read_mostly;
> static bool hwp_boost __read_mostly;
> +static bool hwp_forced __read_mostly;
>
> static struct cpufreq_driver *intel_pstate_driver __read_mostly;
>
> @@ -1705,12 +1706,12 @@ static void intel_pstate_update_epp_defaults(struct cpudata *cpudata)
> return;
>
> /*
> - * If powerup EPP is something other than chipset default 0x80 and
> - * - is more performance oriented than 0x80 (default balance_perf EPP)
> + * If the EPP is set by firmware, which means that firmware enabled HWP
> + * - Is equal or less than 0x80 (default balance_perf EPP)
> * - But less performance oriented than performance EPP
> * then use this as new balance_perf EPP.
> */
> - if (cpudata->epp_default < HWP_EPP_BALANCE_PERFORMANCE &&
> + if (hwp_forced && cpudata->epp_default <= HWP_EPP_BALANCE_PERFORMANCE &&
> cpudata->epp_default > HWP_EPP_PERFORMANCE) {
> epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = cpudata->epp_default;
> return;
> @@ -3423,7 +3424,7 @@ static int __init intel_pstate_init(void)
>
> id = x86_match_cpu(hwp_support_ids);
> if (id) {
> - bool hwp_forced = intel_pstate_hwp_is_enabled();
> + hwp_forced = intel_pstate_hwp_is_enabled();
>
> if (hwp_forced)
> pr_info("HWP enabled by BIOS\n");
> --
Applied as 6.2 material, thanks!
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