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Date:   Thu, 3 Nov 2022 10:48:42 +0530
From:   "Alim Akhtar" <alim.akhtar@...sung.com>
To:     "'Pierre Gondois'" <pierre.gondois@....com>,
        <linux-kernel@...r.kernel.org>
Cc:     <Rob.Herring@....com>, "'Rob Herring'" <robh+dt@...nel.org>,
        "'Krzysztof Kozlowski'" <krzysztof.kozlowski+dt@...aro.org>,
        "'Aswani Reddy'" <aswani.reddy@...sung.com>,
        "'Shashank Prashar'" <s.prashar@...sung.com>,
        "'Sriranjani P'" <sriranjani.p@...sung.com>,
        <devicetree@...r.kernel.org>
Subject: RE: [PATCH 20/20] arm64: dts: Update cache properties for tesla



>-----Original Message-----
>From: Pierre Gondois [mailto:pierre.gondois@....com]
>Sent: Monday, October 31, 2022 2:51 PM
>To: linux-kernel@...r.kernel.org
>Cc: pierre.gondois@....com; Rob.Herring@....com; Rob Herring
><robh+dt@...nel.org>; Krzysztof Kozlowski
><krzysztof.kozlowski+dt@...aro.org>; Alim Akhtar
><alim.akhtar@...sung.com>; Aswani Reddy <aswani.reddy@...sung.com>;
>Shashank Prashar <s.prashar@...sung.com>; Sriranjani P
><sriranjani.p@...sung.com>; devicetree@...r.kernel.org
>Subject: [PATCH 20/20] arm64: dts: Update cache properties for tesla
>
>The DeviceTree Specification v0.3 specifies that the cache node
'compatible'
>and 'cache-level' properties are 'required'. Cf.
>s3.8 Multi-level and Shared Cache Nodes
>
>The recently added init_of_cache_level() function checks these properties.
>Add them if missing.
>
>Signed-off-by: Pierre Gondois <pierre.gondois@....com>
>---
Reviewed-by: Alim Akhtar <alim.akhtar@...sung.com>


> arch/arm64/boot/dts/tesla/fsd.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
>diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi
>b/arch/arm64/boot/dts/tesla/fsd.dtsi
>index f35bc5a288c2..bfab040fc1e4 100644
>--- a/arch/arm64/boot/dts/tesla/fsd.dtsi
>+++ b/arch/arm64/boot/dts/tesla/fsd.dtsi
>@@ -284,6 +284,7 @@ cpucl_l2: l2-cache0 {
> 			cache-size = <0x400000>;
> 			cache-line-size = <64>;
> 			cache-sets = <4096>;
>+			cache-level = <2>;
> 		};
>
> 		idle-states {
>--
>2.25.1


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