linux-kernel - Re: [PATCH 1/2] cxl/pci: Add generic MSI-X/MSI irq support

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Message-ID: <20221103001833.n2gsoflnji3pcsfr@offworld>
Date:   Wed, 2 Nov 2022 17:18:33 -0700
From:   Davidlohr Bueso <dave@...olabs.net>
To:     Ira Weiny <ira.weiny@...el.com>
Cc:     Bjorn Helgaas <helgaas@...nel.org>,
        Jonathan Cameron <Jonathan.Cameron@...wei.com>,
        Dan Williams <dan.j.williams@...el.com>, dave.jiang@...el.com,
        alison.schofield@...el.com, bwidawsk@...nel.org,
        vishal.l.verma@...el.com, a.manzanares@...sung.com,
        linux-cxl@...r.kernel.org, linux-kernel@...r.kernel.org,
        Bjorn Helgaas <bhelgaas@...gle.com>, linux-pci@...r.kernel.org,
        Christoph Hellwig <hch@....de>
Subject: Re: [PATCH 1/2] cxl/pci: Add generic MSI-X/MSI irq support

On Wed, 02 Nov 2022, Ira Weiny wrote:

>On Wed, Nov 02, 2022 at 10:15:24AM -0700, Davidlohr Bueso wrote:
>> Most CXL features that can have irqs will normally use only the first 16,
>> with the exception of isolation (cxl 3.0), which per the spec is up to 32.
>
>Dan, Dave, and I were discussing this and we agree.  For now the only things
>people are working on are within the first 16 so why not just request 16 as the
>max for now?

It is a fair compromise, yes.