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Message-ID: <Y2R/cWkdqlmCGlvC@mailingradian>
Date: Thu, 3 Nov 2022 22:56:49 -0400
From: Richard Acayan <mailingradian@...il.com>
To: Konrad Dybcio <konrad.dybcio@...ainline.org>
Cc: Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Vinod Koul <vkoul@...nel.org>,
Robin Murphy <robin.murphy@....com>,
Chanho Park <chanho61.park@...sung.com>,
Thierry Reding <treding@...dia.com>,
Stephan Gerhold <stephan.gerhold@...nkonzept.com>,
Lorenzo Pieralisi <lpieralisi@...nel.org>,
Robert Marko <robimarko@...il.com>,
Das Srinagesh <quic_gurus@...cinc.com>,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-msm@...r.kernel.org,
~postmarketos/upstreaming@...ts.sr.ht, phone-devel@...r.kernel.org,
Richard Acayan <mailingradian@...il.com>
Subject: Re: [PATCH v2 4/4] arm64: dts: qcom: add sdm670 and pixel 3a device
trees
On Fri, Nov 04, 2022 at 12:49:34AM +0100, Konrad Dybcio wrote:
> On 04/11/2022 00:03, Richard Acayan wrote:
>> The Qualcomm Snapdragon 670 has been out for a while. Add a device tree
>> for it and the Google Pixel 3a as the first device.
>>
>> The Pixel 3a has the same bootloader issue as the Pixel 3 and will not work
>> on Android 10 bootloaders or later until it gets fixed for the Pixel 3.
>>
>> SoC Initial Features:
>> - power management
>> - clocks
>> - pinctrl
>> - eMMC
>> - USB 2.0
>> - GENI I2C
>> - IOMMU
>> - RPMh
>> - interrupts
>>
>> Device-Specific Initial Features:
>> - side buttons (keys)
>> - regulators
>> - touchscreen
>>
>> Signed-off-by: Richard Acayan <mailingradian@...il.com>
>> ---
>> arch/arm64/boot/dts/qcom/Makefile | 1 +
>> .../boot/dts/qcom/sdm670-google-sargo.dts | 532 ++++++++
>> arch/arm64/boot/dts/qcom/sdm670.dtsi | 1169 +++++++++++++++++
>> 3 files changed, 1702 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts
>> create mode 100644 arch/arm64/boot/dts/qcom/sdm670.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
>> index b0558d3389e5..4eb5d8829efb 100644
>> --- a/arch/arm64/boot/dts/qcom/Makefile
>> +++ b/arch/arm64/boot/dts/qcom/Makefile
>> @@ -124,6 +124,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-voyager.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += sdm632-fairphone-fp3.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += sdm636-sony-xperia-ganges-mermaid.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += sdm660-xiaomi-lavender.dtb
>> +dtb-$(CONFIG_ARCH_QCOM) += sdm670-google-sargo.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r1.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r2.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r3.dtb
>> diff --git a/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts
>> new file mode 100644
>> index 000000000000..3a01859dd42c
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts
>> @@ -0,0 +1,532 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Device tree for Google Pixel 3a, adapted from google-blueline device tree,
>> + * xiaomi-lavender device tree, and oneplus-common device tree.
>> + *
>> + * Copyright (c) 2022, Richard Acayan. All rights reserved.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/input/input.h>
>> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
>> +#include <dt-bindings/power/qcom-rpmpd.h>
>> +#include "sdm670.dtsi"
>> +#include "pm660.dtsi"
>> +#include "pm660l.dtsi"
>> +
>> +/delete-node/ &mpss_region;
>> +/delete-node/ &venus_mem;
>> +/delete-node/ &wlan_msa_mem;
>> +/delete-node/ &cdsp_mem;
>> +/delete-node/ &mba_region;
>> +/delete-node/ &adsp_mem;
>> +/delete-node/ &ipa_fw_mem;
>> +/delete-node/ &ipa_gsi_mem;
>> +/delete-node/ &gpu_mem;
>> +
>> +/ {
>> + model = "Google Pixel 3a";
>> + compatible = "google,sargo", "qcom,sdm670";
>> + qcom,board-id = <0x00041e05 0>;
>> + qcom,msm-id = <321 0x20001>;
>> +
>> + aliases { };
>> +
>> + chosen {
>> + stdout-path = "serial0:115200n8";
>> +
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> +
>> + framebuffer@...00000 {
>> + compatible = "simple-framebuffer";
>> + reg = <0x0 0x9c000000 0x0 (1080 * 2220 * 4)>;
>
> Please use '0x0' and '0' consistently in reg properties.
Will also do this in aop_cmd_db_mem because grep works, but not in cpus
because the sm6350 has <0x0 0x0> in cpus and <0x0 0x80000000 0x0 0x0> in
memory. The sdm670 dtsi has <0 0x80000000 0 0>, maybe I should change
that according to other dtsi's already in the kernel.
>
>
>> + width = <1080>;
>> + height = <2220>;
>> + stride = <(1080 * 4)>;
>> + format = "a8r8g8b8";
>> + };
>> + };
>> +
>
> [...]
>
>
>>
>> +
>> +&i2c9 {
>> + clock-frequency = <100000>;
>> + status = "okay";
>> +
>> + synaptics-rmi4-i2c@20 {
>> + compatible = "syna,rmi4-i2c";
>> + reg = <0x20>;
>> + #address-cells = <0x1>;
>> + #size-cells = <0x0>;
>
> #-cells properties should have decimal values.
>
>
> [...]
>
>
>> +};
>> diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi
>> new file mode 100644
>> index 000000000000..cbebe29ca6f8
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi
>> @@ -0,0 +1,1169 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * SDM670 SoC device tree source, adapted from SDM845 SoC device tree
>> + *
>> + * Copyright (c) 2018, The Linux Foundation. All rights reserved.
>> + * Copyright (c) 2022, Richard Acayan. All rights reserved.
>> + */
>> +
>
> [...]
>
>
>> +
>> + gpi_dma0: dma-controller@...000 {
>> + #dma-cells = <3>;
>> + compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma";
>> + reg = <0 0x00800000 0 0x60000>;
>> + interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
>> + dma-channels = <13>;
>> + dma-channel-mask = <0xfa>;
>> + iommus = <&apps_smmu 0x0016 0x0>;
>
> &apps_smmu 0x16 0x0
>
>
> [...]
>> +
>> + intc: interrupt-controller@...00000 {
>> + compatible = "arm,gic-v3";
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> + #interrupt-cells = <3>;
>> + interrupt-controller;
>> + reg = <0 0x17a00000 0 0x10000>, /* GICD */
>> + <0 0x17a60000 0 0x100000>; /* GICR * 8 */
>
> reg second, #cells and ranges last, please.
I'll also move the label property down in apps_rsc and move the #cells
down in touchscreen.
>
>
> Other than that, lgtm
>
>
> Konrad
>
>> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> + };
>> + };
>> +};
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