linux-kernel - Re: [PATCH 02/12] dt-bindings: riscv: Add T-HEAD C906 and C910 compatibles

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Message-ID: <76d9c4fb368dca87c64494b927706d0b18d712d2.camel@icenowy.me>
Date:   Fri, 04 Nov 2022 10:57:58 +0800
From:   Icenowy Zheng <uwu@...nowy.me>
To:     Samuel Holland <samuel@...lland.org>, Chen-Yu Tsai <wens@...e.org>,
        Jernej Skrabec <jernej.skrabec@...il.com>,
        linux-sunxi@...ts.linux.dev, Palmer Dabbelt <palmer@...belt.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        linux-riscv@...ts.infradead.org
Cc:     Rob Herring <robh+dt@...nel.org>, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>
Subject: Re: [PATCH 02/12] dt-bindings: riscv: Add T-HEAD C906 and C910
 compatibles

在 2022-08-15星期一的 00:08 -0500，Samuel Holland写道：
> The C906 and C910 are RISC-V CPU cores from T-HEAD Semiconductor.
> Notably, the C906 core is used in the Allwinner D1 SoC.

Could this get applied first?

C906 and C910 now have a fixed-configuration open-source version, which
means these cores could be played by anyone, and having them in the DT
binding really helps people. In addition I am aware of some C906-
equipped SoC out of Allwinner.

> 
> Signed-off-by: Samuel Holland <samuel@...lland.org>
> ---
> 
>  Documentation/devicetree/bindings/riscv/cpus.yaml | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml
> b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index 873dd12f6e89..ce2161d9115a 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -38,6 +38,8 @@ properties:
>                - sifive,u5
>                - sifive,u7
>                - canaan,k210
> +              - thead,c906
> +              - thead,c910
>            - const: riscv
>        - items:
>            - enum: