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Message-ID: <1c74ac94-50db-ceb3-234d-f8f227de8f6e@linux.dev>
Date: Thu, 3 Nov 2022 22:01:27 -0700
From: Vineet Gupta <vineet.gupta@...ux.dev>
To: Chris Stillson <stillson@...osinc.com>
Cc: Guo Ren <guoren@...ux.alibaba.com>,
Vincent Chen <vincent.chen@...ive.com>,
Han-Kuan Chen <hankuan.chen@...ive.com>,
Greentime Hu <greentime.hu@...ive.com>,
Palmer Dabbelt <palmer@...osinc.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Eric Biederman <ebiederm@...ssion.com>,
Kees Cook <keescook@...omium.org>,
Anup Patel <anup@...infault.org>,
Atish Patra <atishp@...shpatra.org>,
Oleg Nesterov <oleg@...hat.com>,
Heinrich Schuchardt <heinrich.schuchardt@...onical.com>,
Guo Ren <guoren@...nel.org>,
Mayuresh Chitale <mchitale@...tanamicro.com>,
Paolo Bonzini <pbonzini@...hat.com>,
linux-riscv <linux-riscv@...ts.infradead.org>,
lkml <linux-kernel@...r.kernel.org>,
Andy Chiu <andy.chiu@...ive.com>
Subject: Re: [PATCH v12 06/17] riscv: Reset vector register
On 9/21/22 14:43, Chris Stillson wrote:
> From: Guo Ren <guoren@...ux.alibaba.com>
>
> Reset vector registers at boot-time and disable vector instructions
> execution for kernel mode.
Perhaps bike-shedding, but "Reset" has a different connotation in
kernel, this is clear registers IMO. And "Reset Vector ..." sounds
totally different at first glance.
> - * Disable the FPU to detect illegal usage of floating point in kernel
> - * space.
> + * Disable the FPU/Vector to detect illegal usage of floating point
> + * or vector in kernel space.
> */
> - li t0, SR_SUM | SR_FS
> + li t0, SR_SUM | SR_FS | SR_VS
Is VS writable in implementations not implementing V hardware.
Priv spec seems to be confusing. It states
"The FS[1:0] and VS[1:0] WARL fields..."
Above implies it can be written always but will read legal values only.
But then this follows.
"If neither the v registers nor S-mode is implemented, then VS
is read-only zero. If S-mode is implemented but the v registers
are not, VS may optionally be read-only zero"
What does optionally mean for software ?
>
> REG_L s0, TASK_TI_USER_SP(tp)
> csrrc s1, CSR_STATUS, t0
> diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
> index b865046e4dbb..2c81ca42ec4e 100644
> --- a/arch/riscv/kernel/head.S
> +++ b/arch/riscv/kernel/head.S
> @@ -140,10 +140,10 @@ secondary_start_sbi:
> .option pop
>
> /*
> - * Disable FPU to detect illegal usage of
> - * floating point in kernel space
> + * Disable FPU & VECTOR to detect illegal usage of
> + * floating point or vector in kernel space
> */
> - li t0, SR_FS
> + li t0, SR_FS | SR_VS
> csrc CSR_STATUS, t0
>
> /* Set trap vector to spin forever to help debug */
> @@ -234,10 +234,10 @@ pmp_done:
> .option pop
>
> /*
> - * Disable FPU to detect illegal usage of
> - * floating point in kernel space
> + * Disable FPU & VECTOR to detect illegal usage of
> + * floating point or vector in kernel space
> */
> - li t0, SR_FS
> + li t0, SR_FS | SR_VS
> csrc CSR_STATUS, t0
Third instance of duplicated SR_FS | SR_VS. Better to add a helper
SR_FS_VS or some such macro.
>
> #ifdef CONFIG_RISCV_BOOT_SPINWAIT
> @@ -431,6 +431,29 @@ ENTRY(reset_regs)
> csrw fcsr, 0
> /* note that the caller must clear SR_FS */
> #endif /* CONFIG_FPU */
> +
> +#ifdef CONFIG_VECTOR
> + csrr t0, CSR_MISA
> + li t1, COMPAT_HWCAP_ISA_V
> + and t0, t0, t1
> + beqz t0, .Lreset_regs_done
> +
> + /*
> + * Clear vector registers and reset vcsr
> + * VLMAX has a defined value, VLEN is a constant,
> + * and this form of vsetvli is defined to set vl to VLMAX.
> + */
> + li t1, SR_VS
> + csrs CSR_STATUS, t1
> + csrs CSR_VCSR, x0
> + vsetvli t1, x0, e8, m8, ta, ma
> + vmv.v.i v0, 0
> + vmv.v.i v8, 0
> + vmv.v.i v16, 0
> + vmv.v.i v24, 0
> + /* note that the caller must clear SR_VS */
Is that actually happening ?
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