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Message-Id: <bea6eb888717e1c0a3efc58761b0e75e4104f737.1667463263.git.Sandor.yu@nxp.com>
Date: Fri, 4 Nov 2022 14:44:57 +0800
From: Sandor Yu <Sandor.yu@....com>
To: dri-devel@...ts.freedesktop.org, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-phy@...ts.infradead.org, andrzej.hajda@...el.com,
neil.armstrong@...aro.org, robert.foss@...aro.org,
Laurent.pinchart@...asonboard.com, jonas@...boo.se,
jernej.skrabec@...il.com, kishon@...com, vkoul@...nel.org
Cc: robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
shawnguo@...nel.org, s.hauer@...gutronix.de, kernel@...gutronix.de,
linux-imx@....com, tzimmermann@...e.de, lyude@...hat.com,
Sandor.yu@....com, javierm@...hat.com,
ville.syrjala@...ux.intel.com, sam@...nborg.org,
jani.nikula@...el.com, maxime@...no.tech,
penguin-kernel@...ove.SAKURA.ne.jp, p.yadav@...com,
oliver.brown@....com
Subject: [v2 07/10] dts-bindings: phy: Add Cadence HDP-TX DP PHY bindings
Add bindings for Cadence HDP-TX DisplayPort PHY.
Signed-off-by: Sandor Yu <Sandor.yu@....com>
---
.../bindings/phy/phy-cadence-hdptx-dp.yaml | 70 +++++++++++++++++++
1 file changed, 70 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/phy-cadence-hdptx-dp.yaml
diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-hdptx-dp.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-hdptx-dp.yaml
new file mode 100644
index 000000000000..ab6f4e25c425
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-cadence-hdptx-dp.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/phy/phy-cadence-hdptx-dp.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Cadence HDP(HDMI/DisplayPort) TX PHY for DisplayPort protocol binding
+
+description:
+ This binding describes the Cadence HDP-TX PHY for DispalyPort protocol.
+
+maintainers:
+ - Sandor Yu <sandor.yu@....com>
+
+properties:
+ compatible:
+ enum:
+ - cdns,hdptx-dp-phy
+
+ reg:
+ description:
+ Offset of Cadence HDPTX APB configuration registers.
+
+ clocks:
+ items:
+ description:
+ PHY reference clock. Must contain an entry in clock-names.
+
+ clock-names:
+ items:
+ - const: refclk
+
+ "#phy-cells":
+ const: 0
+
+ cdns,num-lanes:
+ description:
+ Number of lanes.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [1, 2, 3, 4]
+ default: 4
+
+ cdns,max-bit-rate:
+ description:
+ Maximum DisplayPort link bit rate to use, in Mbps
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [2160, 2430, 2700, 3240, 4320, 5400]
+ default: 5400
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/phy/phy.h>
+ dp_phy: dp_phy@...00000 {
+ compatible = "cdns,hdptx-dp-phy";
+ reg = <0x32c00000 0x100000>;
+ #phy-cells = <0>;
+ clocks = <&hdmi_phy_27m>;
+ clock-names = "refclk";
+ cdns,num-lanes = <4>;
+ cdns,max-bit-rate = <5400>;
+ };
--
2.34.1
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