linux-kernel - Re: [PATCH 2/2] arm64: dts: qcom: sc8280xp: update UFS PHY nodes

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Date:   Fri, 4 Nov 2022 10:41:48 +0100
From:   Konrad Dybcio <konrad.dybcio@...ainline.org>
To:     Johan Hovold <johan+linaro@...nel.org>,
        Bjorn Andersson <andersson@...nel.org>
Cc:     Andy Gross <agross@...nel.org>, Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Brian Masney <bmasney@...hat.com>,
        Shazad Hussain <quic_shazhuss@...cinc.com>,
        linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH 2/2] arm64: dts: qcom: sc8280xp: update UFS PHY nodes


On 04/11/2022 10:20, Johan Hovold wrote:
> Update the UFS PHY nodes to match the new binding.
>
> Signed-off-by: Johan Hovold <johan+linaro@...nel.org>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@...ainline.org>


Konrad

>   arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 49 +++++++++-----------------
>   1 file changed, 17 insertions(+), 32 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index e0d0fb6994b5..1b309fa93484 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> @@ -896,7 +896,7 @@ ufs_mem_hc: ufs@...4000 {
>   				     "jedec,ufs-2.0";
>   			reg = <0 0x01d84000 0 0x3000>;
>   			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
> -			phys = <&ufs_mem_phy_lanes>;
> +			phys = <&ufs_mem_phy>;
>   			phy-names = "ufsphy";
>   			lanes-per-direction = <2>;
>   			#reset-cells = <1>;
> @@ -937,27 +937,20 @@ ufs_mem_hc: ufs@...4000 {
>   
>   		ufs_mem_phy: phy@...7000 {
>   			compatible = "qcom,sc8280xp-qmp-ufs-phy";
> -			reg = <0 0x01d87000 0 0x1c8>;
> -			#address-cells = <2>;
> -			#size-cells = <2>;
> -			ranges;
> -			clock-names = "ref",
> -				      "ref_aux";
> +			reg = <0 0x01d87000 0 0x1000>;
> +
>   			clocks = <&gcc GCC_UFS_CARD_CLKREF_CLK>,
>   				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
> +			clock-names = "ref", "ref_aux";
> +
> +			power-domains = <&gcc UFS_PHY_GDSC>;
>   
>   			resets = <&ufs_mem_hc 0>;
>   			reset-names = "ufsphy";
> -			status = "disabled";
>   
> -			ufs_mem_phy_lanes: phy@...7400 {
> -				reg = <0 0x01d87400 0 0x108>,
> -				      <0 0x01d87600 0 0x1e0>,
> -				      <0 0x01d87c00 0 0x1dc>,
> -				      <0 0x01d87800 0 0x108>,
> -				      <0 0x01d87a00 0 0x1e0>;
> -				#phy-cells = <0>;
> -			};
> +			#phy-cells = <0>;
> +
> +			status = "disabled";
>   		};
>   
>   		ufs_card_hc: ufs@...4000 {
> @@ -965,7 +958,7 @@ ufs_card_hc: ufs@...4000 {
>   				     "jedec,ufs-2.0";
>   			reg = <0 0x01da4000 0 0x3000>;
>   			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
> -			phys = <&ufs_card_phy_lanes>;
> +			phys = <&ufs_card_phy>;
>   			phy-names = "ufsphy";
>   			lanes-per-direction = <2>;
>   			#reset-cells = <1>;
> @@ -1005,28 +998,20 @@ ufs_card_hc: ufs@...4000 {
>   
>   		ufs_card_phy: phy@...7000 {
>   			compatible = "qcom,sc8280xp-qmp-ufs-phy";
> -			reg = <0 0x01da7000 0 0x1c8>;
> -			#address-cells = <2>;
> -			#size-cells = <2>;
> -			ranges;
> -			clock-names = "ref",
> -				      "ref_aux";
> +			reg = <0 0x01da7000 0 0x1000>;
> +
>   			clocks = <&gcc GCC_UFS_1_CARD_CLKREF_CLK>,
>   				 <&gcc GCC_UFS_CARD_PHY_AUX_CLK>;
> +			clock-names = "ref", "ref_aux";
> +
> +			power-domains = <&gcc UFS_CARD_GDSC>;
>   
>   			resets = <&ufs_card_hc 0>;
>   			reset-names = "ufsphy";
>   
> -			status = "disabled";
> +			#phy-cells = <0>;
>   
> -			ufs_card_phy_lanes: phy@...7400 {
> -				reg = <0 0x01da7400 0 0x108>,
> -				      <0 0x01da7600 0 0x1e0>,
> -				      <0 0x01da7c00 0 0x1dc>,
> -				      <0 0x01da7800 0 0x108>,
> -				      <0 0x01da7a00 0 0x1e0>;
> -				#phy-cells = <0>;
> -			};
> +			status = "disabled";
>   		};
>   
>   		tcsr_mutex: hwlock@...0000 {