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Message-Id: <20221106170555.1580584-6-sashal@kernel.org>
Date: Sun, 6 Nov 2022 12:05:43 -0500
From: Sasha Levin <sashal@...nel.org>
To: linux-kernel@...r.kernel.org, stable@...r.kernel.org
Cc: Mauro Lima <mauro.lima@...ypsium.com>,
Mika Westerberg <mika.westerberg@...ux.intel.com>,
Mark Brown <broonie@...nel.org>,
Sasha Levin <sashal@...nel.org>, tudor.ambarus@...rochip.com,
pratyush@...nel.org, miquel.raynal@...tlin.com, richard@....at,
vigneshr@...com, andriy.shevchenko@...ux.intel.com,
lee.jones@...aro.org, linux-mtd@...ts.infradead.org
Subject: [PATCH AUTOSEL 5.10 06/16] spi: intel: Fix the offset to get the 64K erase opcode
From: Mauro Lima <mauro.lima@...ypsium.com>
[ Upstream commit 6a43cd02ddbc597dc9a1f82c1e433f871a2f6f06 ]
According to documentation, the 64K erase opcode is located in VSCC
range [16:23] instead of [8:15].
Use the proper value to shift the mask over the correct range.
Signed-off-by: Mauro Lima <mauro.lima@...ypsium.com>
Reviewed-by: Mika Westerberg <mika.westerberg@...ux.intel.com>
Link: https://lore.kernel.org/r/20221012152135.28353-1-mauro.lima@eclypsium.com
Signed-off-by: Mark Brown <broonie@...nel.org>
Signed-off-by: Sasha Levin <sashal@...nel.org>
---
drivers/mtd/spi-nor/controllers/intel-spi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/controllers/intel-spi.c b/drivers/mtd/spi-nor/controllers/intel-spi.c
index b54a56a68100..b4b0affd16c8 100644
--- a/drivers/mtd/spi-nor/controllers/intel-spi.c
+++ b/drivers/mtd/spi-nor/controllers/intel-spi.c
@@ -117,7 +117,7 @@
#define ERASE_OPCODE_SHIFT 8
#define ERASE_OPCODE_MASK (0xff << ERASE_OPCODE_SHIFT)
#define ERASE_64K_OPCODE_SHIFT 16
-#define ERASE_64K_OPCODE_MASK (0xff << ERASE_OPCODE_SHIFT)
+#define ERASE_64K_OPCODE_MASK (0xff << ERASE_64K_OPCODE_SHIFT)
#define INTEL_SPI_TIMEOUT 5000 /* ms */
#define INTEL_SPI_FIFO_SZ 64
--
2.35.1
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