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Message-Id: <20221107155825.1644604-8-pierre.gondois@arm.com>
Date: Mon, 7 Nov 2022 16:57:00 +0100
From: Pierre Gondois <pierre.gondois@....com>
To: linux-kernel@...r.kernel.org
Cc: Pierre Gondois <pierre.gondois@....com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Florian Fainelli <f.fainelli@...il.com>,
Broadcom internal kernel review list
<bcm-kernel-feedback-list@...adcom.com>,
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Scott Branden <sbranden@...adcom.com>,
Tsahee Zidenberg <tsahee@...apurnalabs.com>,
Antoine Tenart <atenart@...nel.org>,
Brijesh Singh <brijeshkumar.singh@....com>,
Suravee Suthikulpanit <suravee.suthikulpanit@....com>,
Tom Lendacky <thomas.lendacky@....com>,
Neil Armstrong <neil.armstrong@...aro.org>,
Kevin Hilman <khilman@...libre.com>,
Jerome Brunet <jbrunet@...libre.com>,
Martin Blumenstingl <martin.blumenstingl@...glemail.com>,
Khuong Dinh <khuong@...amperecomputing.com>,
Liviu Dudau <liviu.dudau@....com>,
Sudeep Holla <sudeep.holla@....com>,
Lorenzo Pieralisi <lpieralisi@...nel.org>,
William Zhang <william.zhang@...adcom.com>,
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Kursad Oney <kursad.oney@...adcom.com>,
Rafał Miłecki <rafal@...ecki.pl>,
Alim Akhtar <alim.akhtar@...sung.com>,
Shawn Guo <shawnguo@...nel.org>, Li Yang <leoyang.li@....com>,
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Andreas Färber <afaerber@...e.de>,
Matthias Brugger <mbrugger@...e.com>,
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Wei Xu <xuwei5@...ilicon.com>, Chanho Min <chanho.min@....com>,
Andrew Lunn <andrew@...n.ch>,
Gregory Clement <gregory.clement@...tlin.com>,
Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>,
Lars Povlsen <lars.povlsen@...rochip.com>,
Steen Hegelund <Steen.Hegelund@...rochip.com>,
Daniel Machon <daniel.machon@...rochip.com>,
UNGLinuxDriver@...rochip.com, Avi Fishman <avifishman70@...il.com>,
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Jacky Bai <ping.bai@....com>, Wei Fang <wei.fang@....com>,
Chris Packham <chris.packham@...iedtelesis.co.nz>,
Vadym Kochan <vadym.kochan@...ision.eu>,
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Prathamesh Shete <pshete@...dia.com>,
Akhil R <akhilrajeev@...dia.com>,
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Christopher Obbard <chris.obbard@...labora.com>,
Ezequiel Garcia <ezequiel@...guardiasur.com.ar>,
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Shashank Prashar <s.prashar@...sung.com>,
Sriranjani P <sriranjani.p@...sung.com>,
devicetree@...r.kernel.org, linux-rpi-kernel@...ts.infradead.org,
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linux-amlogic@...ts.infradead.org,
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Subject: [PATCH v2 07/23] arm64: dts: Update cache properties for exynos
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@....com>
---
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 4 ++++
arch/arm64/boot/dts/exynos/exynos7.dtsi | 2 ++
2 files changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index bd6a354b9cb5..8619920da4b6 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -226,6 +226,8 @@ cpu7: cpu@3 {
cluster_a57_l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
@@ -233,6 +235,8 @@ cluster_a57_l2: l2-cache0 {
cluster_a53_l2: l2-cache1 {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
cache-size = <0x40000>;
cache-line-size = <64>;
cache-sets = <256>;
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 1cd771c90b47..f378d8629d88 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -107,6 +107,8 @@ cpu_atlas3: cpu@3 {
atlas_l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
--
2.25.1
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