linux-kernel - Re: [PATCH 2/2] dt-bindings: interrupt-controller: add yaml for LoongArch CPU interrupt controller

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <37f77670-f8c3-5fbf-c84f-eeaa85107c5a@loongson.cn>
Date:   Mon, 7 Nov 2022 20:12:56 +0800
From:   Liu Peibao <liupeibao@...ngson.cn>
To:     Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Marc Zyngier <maz@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Huacai Chen <chenhuacai@...nel.org>,
        WANG Xuerui <kernel@...0n.name>
Cc:     Jianmin Lv <lvjianmin@...ngson.cn>,
        Yinbo Zhu <zhuyinbo@...ngson.cn>, linux-mips@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH 2/2] dt-bindings: interrupt-controller: add yaml for
 LoongArch CPU interrupt controller

On 11/7/22 7:33 PM, Krzysztof Kozlowski wrote:
>>>>>> +    const: loongarch,cpu-interrupt-controller
>>>>>
>>>>> You have exactly one and only one type of CPU interrupt controller for
>>>>> all your Loongarch designs? All current and all future? All?
>>>>>
>>>>
>>>> It is sure of that "all current and recent designs". It is really hard to limit the
>>>> design in the distant future.
>>>>
>>>> And if there is updating, maybe I will add additional things like this:
>>>> "loongarch,cpu-interrupt-controller-2.0".
>>>
>>> Unless you have a clear versioning of your hardware, adding 2.0 won't be
>>> correct. Don't you have this for specific SoC?
>>>
>>
>> The "loongarch,cpu-interrupt-controller" now is compatible for all the LoongArch
>> compatible CPUs, not specific for one chip. And we may keep this CPU interrupt
>> controller for a long time.
> 
> Still specific compatibles (as fallbacks) are used for such cases, so
> why is this different? Hardware compatible with several other devices
> still gets specific compatible, right?
>

I don't really agree with that. This is a specified higher level abstract of all
our designed hardware. We could do this as we have unified this in hardware. So
this compatible could be simple.
 
> You cannot have "-2.0" suffix in the future just because "you want", so
> be sure that your choice is reasonable.
> 

It was an example and the CPUs IRQs hardware updating is not on our schedule.
If I do some thing like "-2.0" in the future, I will find a proper way and
be reasonable.

BR,
Peibao