linux-kernel - Re: [PATCH v3 3/8] arm64/sysreg: Convert SPE registers to automatic generation

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <Y2kgC9QlBwvXTLe6@sirena.org.uk>
Date:   Mon, 7 Nov 2022 15:11:07 +0000
From:   Mark Brown <broonie@...nel.org>
To:     Rob Herring <robh@...nel.org>
Cc:     Namhyung Kim <namhyung@...nel.org>, Will Deacon <will@...nel.org>,
        Arnaldo Carvalho de Melo <acme@...nel.org>,
        Jiri Olsa <jolsa@...nel.org>,
        Peter Zijlstra <peterz@...radead.org>,
        Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
        Mark Rutland <mark.rutland@....com>,
        Catalin Marinas <catalin.marinas@....com>,
        Marc Zyngier <maz@...nel.org>,
        Oliver Upton <oliver.upton@...ux.dev>,
        Ingo Molnar <mingo@...hat.com>,
        Suzuki K Poulose <suzuki.poulose@....com>,
        James Morse <james.morse@....com>,
        Alexandru Elisei <alexandru.elisei@....com>,
        kvmarm@...ts.linux.dev, linux-perf-users@...r.kernel.org,
        linux-kernel@...r.kernel.org, James Clark <james.clark@....com>,
        linux-arm-kernel@...ts.infradead.org, kvmarm@...ts.cs.columbia.edu
Subject: Re: [PATCH v3 3/8] arm64/sysreg: Convert SPE registers to automatic
 generation

On Fri, Nov 04, 2022 at 10:55:03AM -0500, Rob Herring wrote:

> Convert all the SPE register defines to automatic generation. No
> functional changes.
> 
> New registers and fields for SPEv1.2 are added with the conversion.
> 
> Some of the PMBSR MSS field defines are kept as the automatic generation
> has no way to create multiple names for the same register bits. The
> meaning of the MSS field depends on other bits.

Reviewed-by: Mark Brown <broonie@...nel.org>

> +Sysreg	PMSNEVFR_EL1	3	0	9	9	1
> +Field	63:0	E
> +EndSysreg

JFTR as noted last time this looks nothing like the spec but is clearly
a sensible interpretation.

I do note that one advantage of doing this register by register rather
than en masse is that it makes it a lot easier to avoid re-reviewing the
same register...

Download attachment "signature.asc" of type "application/pgp-signature" (489 bytes)