linux-kernel - Re: [PATCH v5 0/7] Add support for Renesas RZ/Five SoC

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Date:   Tue, 8 Nov 2022 19:29:04 +0000
From:   Conor Dooley <conor@...nel.org>
To:     Geert Uytterhoeven <geert@...ux-m68k.org>
Cc:     "Lad, Prabhakar" <prabhakar.csengg@...il.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Magnus Damm <magnus.damm@...il.com>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Heiko Stuebner <heiko@...ech.de>,
        Conor Dooley <conor.dooley@...rochip.com>,
        Guo Ren <guoren@...nel.org>, Anup Patel <anup@...infault.org>,
        Atish Patra <atishp@...osinc.com>,
        Heinrich Schuchardt <heinrich.schuchardt@...onical.com>,
        devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org,
        linux-kernel@...r.kernel.org, linux-renesas-soc@...r.kernel.org,
        Biju Das <biju.das.jz@...renesas.com>,
        Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH v5 0/7] Add support for Renesas RZ/Five SoC

On Tue, Nov 08, 2022 at 05:02:57PM +0100, Geert Uytterhoeven wrote:
> Hi Conor,
> On Mon, Nov 7, 2022 at 7:17 PM Conor Dooley <conor@...nel.org> wrote:
> > Geert, are you waiting for an ack from Palmer?
> 
> I can take:
>   - [PATCH v5 4/7] riscv: dts: renesas: Add initial devicetree for
> Renesas RZ/Five SoC
>   - [PATCH v5 5/7] riscv: dts: renesas: Add minimal DTS for Renesas
> RZ/Five SMARC EVK
>   - [PATCH v5 6/7] MAINTAINERS: Add entry for Renesas RISC-V
> (4/7 and 5/7 depend on my renesas-arm-dt-for-v6.2 branch) and funnel
> them to the SoC-people.
> 
> I can take
>   - [PATCH v5 3/7] riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option
>   - [PATCH v5 7/7] riscv: configs: defconfig: Enable Renesas RZ/Five SoC
> with an ack from Palmer.
> 
> The rest
>   - [PATCH v5 1/7] dt-bindings: riscv: Sort the CPU core list alphabetically
>   - [PATCH v5 2/7] dt-bindings: riscv: Add Andes AX45MP core to the list
> should probably go through the riscv tree, to avoid merge conflicts
> when support for other SoCs is added?

Or depending on the outcome of [0], maybe I take the dt-binding stuff?

Either way, looks like an ack from Palmer is needed for 3 & 7. I can do
the video call version of a ping on that tomorrow at the pw sync thing.

[0] - https://lore.kernel.org/linux-riscv/Y2puchRvbo6+YJSy@wendy/T/#me49f1e779dee210d3ab6fc4bc308dbaed036e1a8