linux-kernel - Re: [PATCH 3/3] x86/pm: Add enumeration check before spec MSRs save/restore setup

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Message-ID: <20221108220931.3bavijj6adclj4sj@desk>
Date:   Tue, 8 Nov 2022 14:09:31 -0800
From:   Pawan Gupta <pawan.kumar.gupta@...ux.intel.com>
To:     Dave Hansen <dave.hansen@...el.com>
Cc:     Thomas Gleixner <tglx@...utronix.de>,
        Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>,
        Dave Hansen <dave.hansen@...ux.intel.com>, x86@...nel.org,
        "H. Peter Anvin" <hpa@...or.com>,
        "Rafael J. Wysocki" <rafael@...nel.org>,
        Pavel Machek <pavel@....cz>,
        Andrew Cooper <Andrew.Cooper3@...rix.com>, degoede@...hat.com,
        linux-kernel@...r.kernel.org, linux-pm@...r.kernel.org,
        Daniel Sneddon <daniel.sneddon@...ux.intel.com>,
        antonio.gomez.iglesias@...ux.intel.com
Subject: Re: [PATCH 3/3] x86/pm: Add enumeration check before spec MSRs
 save/restore setup

On Tue, Nov 08, 2022 at 10:40:06AM -0800, Dave Hansen wrote:
>On 9/12/22 16:41, Pawan Gupta wrote:
>> On an Intel Atom N2600 (and presumable other Cedar Trail models)
>> MSR_IA32_TSX_CTRL can be read, causing saved_msr.valid to be set for it
>> by msr_build_context().
>
>This changelog needs some help.  Shouldn't it be something like this?
>
>pm_save_spec_msr() keeps a list of all the MSRs which _might_ need to be
>saved and restored at hibernate?? and resume??.  However, it has zero
>awareness of CPU support for these MSRs.  It mostly works by
>unconditionally attempting to manipulate these MSRs and relying on
>rdmsrl_safe() being able to handle a #GP on CPUs where the support is
>unavailable.
>
>However, it's possible for reads (RDMSR) to be supported for a given MSR
>while writes (WRMSR) are not.  In this case, msr_build_context() sees a
>successful read (RDMSR) and marks the MSR as 'valid'.  Then, later, a
>write (WRMSR) fails, producing a nasty (but harmless) error message.
>
>To fix this, add the corresponding X86_FEATURE bit for each MSR.  Avoid
>trying to manipulate the MSR when the feature bit is clear.  This
>required adding a X86_FEATURE bit for MSRs that do not have one already,
>but it's a small price to pay.

Yes, that's a lot better. Thanks.