linux-kernel - RE: [PATCH RFC 2/5] pinctrl: renesas: rzg2l: Fix configuring the GPIO pins as interrupts

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Date:   Tue, 8 Nov 2022 07:14:14 +0000
From:   Biju Das <biju.das.jz@...renesas.com>
To:     Prabhakar <prabhakar.csengg@...il.com>,
        Thomas Gleixner <tglx@...utronix.de>,
        Marc Zyngier <maz@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Geert Uytterhoeven <geert+renesas@...der.be>,
        Magnus Damm <magnus.damm@...il.com>,
        Linus Walleij <linus.walleij@...aro.org>
CC:     "linux-gpio@...r.kernel.org" <linux-gpio@...r.kernel.org>,
        "linux-renesas-soc@...r.kernel.org" 
        <linux-renesas-soc@...r.kernel.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: RE: [PATCH RFC 2/5] pinctrl: renesas: rzg2l: Fix configuring the GPIO
 pins as interrupts

Hi Prabhakar,


> Subject: [PATCH RFC 2/5] pinctrl: renesas: rzg2l: Fix configuring the GPIO
> pins as interrupts
> 
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> 
> On the RZ/G2UL SoC we have less number of pins compared to RZ/G2L and also
> the pin configs are completely different. This patch makes sure we use the
> appropriate pin configs for each SoC (which is passed as part of the OF
> data) while configuring the GPIO pin as interrupts instead of using
> rzg2l_gpio_configs[] for all the SoCs.
> 

Looks like you are missing fixes tag.
Fixes: db2e5f21a48ed ("pinctrl: renesas: pinctrl-rzg2l: Add IRQ domain to handle GPIO interrupt")

As we have already pinctrl support for RZ/G2UL [1]
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/pinctrl/renesas/pinctrl-rzg2l.c?h=v6.1-rc4&id=bfc69bdbaad141ac408e6de86b7e0d771c8e3ccb

Cheers,
Biju

> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> ---
>  drivers/pinctrl/renesas/pinctrl-rzg2l.c | 17 ++++++++++-------
>  1 file changed, 10 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> index a43824fd9505..dcc495baa678 100644
> --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> @@ -127,6 +127,7 @@ struct rzg2l_dedicated_configs {  struct
> rzg2l_pinctrl_data {
>  	const char * const *port_pins;
>  	const u32 *port_pin_configs;
> +	unsigned int n_port_pin_configs;
>  	struct rzg2l_dedicated_configs *dedicated_pins;
>  	unsigned int n_port_pins;
>  	unsigned int n_dedicated_pins;
> @@ -1122,7 +1123,7 @@ static struct {
>  	}
>  };
> 
> -static int rzg2l_gpio_get_gpioint(unsigned int virq)
> +static int rzg2l_gpio_get_gpioint(unsigned int virq, const struct
> +rzg2l_pinctrl_data *data)
>  {
>  	unsigned int gpioint;
>  	unsigned int i;
> @@ -1131,13 +1132,13 @@ static int rzg2l_gpio_get_gpioint(unsigned int virq)
>  	port = virq / 8;
>  	bit = virq % 8;
> 
> -	if (port >= ARRAY_SIZE(rzg2l_gpio_configs) ||
> -	    bit >= RZG2L_GPIO_PORT_GET_PINCNT(rzg2l_gpio_configs[port]))
> +	if (port >= data->n_port_pin_configs ||
> +	    bit >= RZG2L_GPIO_PORT_GET_PINCNT(data->port_pin_configs[port]))
>  		return -EINVAL;
> 
>  	gpioint = bit;
>  	for (i = 0; i < port; i++)
> -		gpioint += RZG2L_GPIO_PORT_GET_PINCNT(rzg2l_gpio_configs[i]);
> +		gpioint += RZG2L_GPIO_PORT_GET_PINCNT(data->port_pin_configs[i]);
> 
>  	return gpioint;
>  }
> @@ -1237,7 +1238,7 @@ static int rzg2l_gpio_child_to_parent_hwirq(struct
> gpio_chip *gc,
>  	unsigned long flags;
>  	int gpioint, irq;
> 
> -	gpioint = rzg2l_gpio_get_gpioint(child);
> +	gpioint = rzg2l_gpio_get_gpioint(child, pctrl->data);
>  	if (gpioint < 0)
>  		return gpioint;
> 
> @@ -1311,8 +1312,8 @@ static void rzg2l_init_irq_valid_mask(struct gpio_chip
> *gc,
>  		port = offset / 8;
>  		bit = offset % 8;
> 
> -		if (port >= ARRAY_SIZE(rzg2l_gpio_configs) ||
> -		    bit >= RZG2L_GPIO_PORT_GET_PINCNT(rzg2l_gpio_configs[port]))
> +		if (port >= pctrl->data->n_port_pin_configs ||
> +		    bit >=
> +RZG2L_GPIO_PORT_GET_PINCNT(pctrl->data->port_pin_configs[port]))
>  			clear_bit(offset, valid_mask);
>  	}
>  }
> @@ -1517,6 +1518,7 @@ static int rzg2l_pinctrl_probe(struct platform_device
> *pdev)  static struct rzg2l_pinctrl_data r9a07g043_data = {
>  	.port_pins = rzg2l_gpio_names,
>  	.port_pin_configs = r9a07g043_gpio_configs,
> +	.n_port_pin_configs = ARRAY_SIZE(r9a07g043_gpio_configs),
>  	.dedicated_pins = rzg2l_dedicated_pins.common,
>  	.n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) *
> RZG2L_PINS_PER_PORT,
>  	.n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common),
> @@ -1525,6 +1527,7 @@ static struct rzg2l_pinctrl_data r9a07g043_data = {
> static struct rzg2l_pinctrl_data r9a07g044_data = {
>  	.port_pins = rzg2l_gpio_names,
>  	.port_pin_configs = rzg2l_gpio_configs,
> +	.n_port_pin_configs = ARRAY_SIZE(rzg2l_gpio_configs),
>  	.dedicated_pins = rzg2l_dedicated_pins.common,
>  	.n_port_pins = ARRAY_SIZE(rzg2l_gpio_names),
>  	.n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) +
> --
> 2.25.1