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Message-ID: <20221108155906.3pssiipdfrm55q56@bogus>
Date: Tue, 8 Nov 2022 15:59:06 +0000
From: Sudeep Holla <sudeep.holla@....com>
To: Conor Dooley <conor.dooley@...rochip.com>
Cc: Pierre Gondois <pierre.gondois@....com>,
linux-kernel@...r.kernel.org,
Catalin Marinas <catalin.marinas@....com>,
Will Deacon <will@...nel.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
"Rafael J. Wysocki" <rafael@...nel.org>,
Len Brown <lenb@...nel.org>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Gavin Shan <gshan@...hat.com>,
Krzysztof WilczyĆski <kw@...ux.com>,
Jani Nikula <jani.nikula@...el.com>,
Jakub Kicinski <kuba@...nel.org>,
linux-arm-kernel@...ts.infradead.org,
linux-riscv@...ts.infradead.org, linux-acpi@...r.kernel.org
Subject: Re: [PATCH 1/5] cacheinfo: Use riscv's init_cache_level() as generic
OF implem
On Tue, Nov 08, 2022 at 02:07:41PM +0000, Conor Dooley wrote:
> On Tue, Nov 08, 2022 at 12:04:17PM +0100, Pierre Gondois wrote:
> > Riscv's implementation of init_of_cache_level() is following
>
> heh, "Riscv" always looks a bit odd!
> Code movement looks fine, nothing surface level is broken on RISC-V.
> Reviewed-by: Conor Dooley <conor.dooley@...rochip.com>
>
Thanks for the review and testing. I was planning to ask Pierre to cc you
next time but you seem to have covered that for me :).
--
Regards,
Sudeep
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