linux-kernel - Re: [PATCH 2/3] x86/cpu/amd: Add feature bit for MSR_AMD64_LS

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Message-ID: <1ee02d57-21a7-b18e-6cf9-0667445a6fb3@citrix.com>
Date:   Wed, 9 Nov 2022 00:45:58 +0000
From:   Andrew Cooper <Andrew.Cooper3@...rix.com>
To:     Borislav Petkov <bp@...en8.de>,
        Pawan Gupta <pawan.kumar.gupta@...ux.intel.com>
CC:     Thomas Gleixner <tglx@...utronix.de>,
        Ingo Molnar <mingo@...hat.com>,
        Dave Hansen <dave.hansen@...ux.intel.com>,
        "x86@...nel.org" <x86@...nel.org>,
        "H. Peter Anvin" <hpa@...or.com>,
        "Rafael J. Wysocki" <rafael@...nel.org>,
        Pavel Machek <pavel@....cz>,
        "hdegoede@...hat.com" <hdegoede@...hat.com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux-pm@...r.kernel.org" <linux-pm@...r.kernel.org>,
        Daniel Sneddon <daniel.sneddon@...ux.intel.com>,
        "antonio.gomez.iglesias@...ux.intel.com" 
        <antonio.gomez.iglesias@...ux.intel.com>,
        Andrew Cooper <Andrew.Cooper3@...rix.com>
Subject: Re: [PATCH 2/3] x86/cpu/amd: Add feature bit for MSR_AMD64_LS_CFG
 enumeration

On 08/11/2022 23:10, Borislav Petkov wrote:
> On Tue, Nov 08, 2022 at 02:51:41PM -0800, Pawan Gupta wrote:
>> Looking at bsp_init_amd() this feature bit will only be set on AMD
>> families 0x15-0x17. Andrew mentioned that the MSR LS_CFG is present on
>> AMD family >= 0x10 && family <= 0x18.
> Do you need to save that MSR on those families?
>
> Or do 0x15-0x18 suffice?
>
> Yes, 0x18 because that's Hygon and that does its own detection.
>
> So, do you need to save it on families 0x10-0x14?

https://www.amd.com/system/files/documents/software-techniques-for-managing-speculation.pdf 
Mitigation G-2.

The MSR exists on Fam 10/12/14/15/16/17, and in all cases the
LFENCE_DISPATCH bit wants setting if not already set.

The MSR is missing on Fam 0f/11 but these parts already have the wanted
behaviour.

~Andrew