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Message-ID: <20221109104059.766720-2-rrichter@amd.com>
Date: Wed, 9 Nov 2022 11:40:51 +0100
From: Robert Richter <rrichter@....com>
To: Alison Schofield <alison.schofield@...el.com>,
Vishal Verma <vishal.l.verma@...el.com>,
Ira Weiny <ira.weiny@...el.com>,
Ben Widawsky <bwidawsk@...nel.org>,
Dan Williams <dan.j.williams@...el.com>
CC: <linux-cxl@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
Bjorn Helgaas <bhelgaas@...gle.com>,
"Rafael J. Wysocki" <rafael@...nel.org>,
Len Brown <lenb@...nel.org>,
Jonathan Cameron <Jonathan.Cameron@...wei.com>,
"Davidlohr Bueso" <dave@...olabs.net>,
Dave Jiang <dave.jiang@...el.com>,
Robert Richter <rrichter@....com>
Subject: [PATCH v3 1/9] cxl/acpi: Register CXL host ports by bridge device
A port of a CXL host bridge links to the bridge's acpi device
(&adev->dev) with its corresponding uport/dport device (uport_dev and
dport_dev respectively). The device is not a direct parent device in
the PCI topology as pdev->dev.parent points to a PCI bridge's (struct
pci_host_bridge) device. The following CXL memory device hierarchy
would be valid for an endpoint once an RCD EP would be enabled (note
this will be done in a later patch):
VH mode:
cxlmd->dev.parent->parent
^^^\^^^^^^\ ^^^^^^\
\ \ pci_dev (Type 1, Downstream Port)
\ pci_dev (Type 0, PCI Express Endpoint)
cxl mem device
RCD mode:
cxlmd->dev.parent->parent
^^^\^^^^^^\ ^^^^^^\
\ \ pci_host_bridge
\ pci_dev (Type 0, RCiEP)
cxl mem device
In VH mode a downstream port is created by port enumeration and thus
always exists.
Now, in RCD mode the host bridge also already exists but it references
to an ACPI device. A port lookup by the PCI device's parent device
will fail as a direct link to the registered port is missing. The ACPI
device of the bridge must be determined first.
To prevent this, change port registration of a CXL host to use the
bridge device instead. Do this also for the VH case as port topology
will better reflect the PCI topology then.
If a mock device is registered by a test driver, the bridge pointer
can be NULL. Keep using the matching ACPI device (&adev->dev) as a
fallback in this case.
Signed-off-by: Robert Richter <rrichter@....com>
---
drivers/cxl/acpi.c | 48 ++++++++++++++++++++++++++++++----------------
1 file changed, 31 insertions(+), 17 deletions(-)
diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c
index fb9f72813067..06150c953f58 100644
--- a/drivers/cxl/acpi.c
+++ b/drivers/cxl/acpi.c
@@ -185,6 +185,17 @@ __mock struct acpi_device *to_cxl_host_bridge(struct device *host,
return NULL;
}
+static inline struct acpi_pci_root *to_cxl_pci_root(struct device *host,
+ struct device *match)
+{
+ struct acpi_device *adev = to_cxl_host_bridge(host, match);
+
+ if (!adev)
+ return NULL;
+
+ return acpi_pci_find_root(adev->handle);
+}
+
/*
* A host bridge is a dport to a CFMWS decode and it is a uport to the
* dport (PCIe Root Ports) in the host bridge.
@@ -193,35 +204,35 @@ static int add_host_bridge_uport(struct device *match, void *arg)
{
struct cxl_port *root_port = arg;
struct device *host = root_port->dev.parent;
- struct acpi_device *bridge = to_cxl_host_bridge(host, match);
- struct acpi_pci_root *pci_root;
+ struct acpi_pci_root *pci_root = to_cxl_pci_root(host, match);
struct cxl_dport *dport;
struct cxl_port *port;
+ struct device *bridge;
int rc;
- if (!bridge)
+ if (!pci_root)
return 0;
- dport = cxl_find_dport_by_dev(root_port, match);
+ /*
+ * If it is a mock dev, the bridge can be NULL, use matching
+ * device (&adev->dev) as a fallback then then.
+ */
+ bridge = pci_root->bus->bridge ?: match;
+ dport = cxl_find_dport_by_dev(root_port, bridge);
if (!dport) {
dev_dbg(host, "host bridge expected and not found\n");
return 0;
}
- /*
- * Note that this lookup already succeeded in
- * to_cxl_host_bridge(), so no need to check for failure here
- */
- pci_root = acpi_pci_find_root(bridge->handle);
- rc = devm_cxl_register_pci_bus(host, match, pci_root->bus);
+ rc = devm_cxl_register_pci_bus(host, bridge, pci_root->bus);
if (rc)
return rc;
- port = devm_cxl_add_port(host, match, dport->component_reg_phys, dport);
+ port = devm_cxl_add_port(host, bridge, dport->component_reg_phys, dport);
if (IS_ERR(port))
return PTR_ERR(port);
- dev_info(pci_root->bus->bridge, "host supports CXL\n");
+ dev_info(bridge, "host supports CXL\n");
return 0;
}
@@ -258,13 +269,16 @@ static int add_host_bridge_dport(struct device *match, void *arg)
struct cxl_chbs_context ctx;
struct cxl_port *root_port = arg;
struct device *host = root_port->dev.parent;
- struct acpi_device *bridge = to_cxl_host_bridge(host, match);
+ struct acpi_pci_root *pci_root = to_cxl_pci_root(host, match);
+ struct device *bridge;
+ acpi_handle handle;
- if (!bridge)
+ if (!pci_root)
return 0;
- status = acpi_evaluate_integer(bridge->handle, METHOD_NAME__UID, NULL,
- &uid);
+ bridge = pci_root->bus->bridge ?: match;
+ handle = pci_root->device->handle;
+ status = acpi_evaluate_integer(handle, METHOD_NAME__UID, NULL, &uid);
if (status != AE_OK) {
dev_err(match, "unable to retrieve _UID\n");
return -ENODEV;
@@ -285,7 +299,7 @@ static int add_host_bridge_dport(struct device *match, void *arg)
dev_dbg(match, "CHBCR found: 0x%08llx\n", (u64)ctx.chbcr);
- dport = devm_cxl_add_dport(root_port, match, uid, ctx.chbcr);
+ dport = devm_cxl_add_dport(root_port, bridge, uid, ctx.chbcr);
if (IS_ERR(dport))
return PTR_ERR(dport);
--
2.30.2
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