lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Wed, 9 Nov 2022 12:20:38 +0100
From:   Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To:     Vivek Yadav <vivek.2311@...sung.com>, rcsekar@...sung.com,
        krzysztof.kozlowski+dt@...aro.org, wg@...ndegger.com,
        mkl@...gutronix.de, davem@...emloft.net, edumazet@...gle.com,
        kuba@...nel.org, pabeni@...hat.com, pankaj.dubey@...sung.com,
        ravi.patel@...sung.com, alim.akhtar@...sung.com,
        linux-fsd@...la.com, robh+dt@...nel.org
Cc:     linux-can@...r.kernel.org, netdev@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-samsung-soc@...r.kernel.org, devicetree@...r.kernel.org,
        aswani.reddy@...sung.com, sriranjani.p@...sung.com
Subject: Re: [PATCH v2 5/6] can: m_can: Add ECC functionality for message RAM

On 09/11/2022 11:09, Vivek Yadav wrote:
> Whenever MCAN Buffers and FIFOs are stored on message ram, there are
> inherent risks of corruption known as single-bit errors.
> 
> Enable error correction code (ECC) data integrity check for Message RAM
> to create valid ECC checksums.
> 
> ECC uses a respective number of bits, which are added to each word as a
> parity and that will raise the error signal on the corruption in the
> Interrupt Register(IR).
> 
> This indicates either bit error detected and Corrected(BEC) or No bit
> error detected when reading from Message RAM.
> 
> Signed-off-by: Chandrasekar R <rcsekar@...sung.com>
> Signed-off-by: Vivek Yadav <vivek.2311@...sung.com>

(...)

>  
> +static int m_can_plat_init(struct m_can_classdev *cdev)
> +{
> +	struct  m_can_ecc_regmap *ecc_cfg = &cdev->ecc_cfg_sys;
> +	struct device_node *np = cdev->dev->of_node;
> +	int ret = 0;
> +
> +	if (cdev->mram_cfg_flag != ECC_ENABLE) {
> +		/* Initialize mcan message ram */
> +		ret = m_can_init_ram(cdev);
> +
> +		if (ret)
> +			return ret;
> +
> +		cdev->mram_cfg_flag = ECC_ENABLE;
> +	}
> +
> +	if (ecc_cfg->ecc_cfg_flag != ECC_ENABLE) {
> +		/* configure error code check for mram */
> +		if (!ecc_cfg->syscon) {
> +			ecc_cfg->syscon =
> +			syscon_regmap_lookup_by_phandle_args(np,
> +							     "tesla,mram-ecc-cfg"
> +							     , 1,

, goes to previous line

> +							     &ecc_cfg->reg);
> +		}
> +
> +		if (IS_ERR(ecc_cfg->syscon)) {
> +			dev_err(cdev->dev, "couldn't get the syscon reg!\n");

Didn't you just break all platforms using ECC?

Best regards,
Krzysztof

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ