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Message-ID: <AM9PR04MB8506F52B7E88ED1FE64554A1E2019@AM9PR04MB8506.eurprd04.prod.outlook.com>
Date:   Thu, 10 Nov 2022 08:51:43 +0000
From:   Jan Petrous <jan.petrous@....com>
To:     Andrew Lunn <andrew@...n.ch>
CC:     Chester Lin <clin@...e.com>,
        Andreas Färber <afaerber@...e.de>,
        Rob Herring <robh@...nel.org>,
        "David S. Miller" <davem@...emloft.net>,
        Eric Dumazet <edumazet@...gle.com>,
        Jakub Kicinski <kuba@...nel.org>,
        Paolo Abeni <pabeni@...hat.com>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        dl-S32 <S32@....com>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        Matthias Brugger <mbrugger@...e.com>
Subject: RE: [EXT] Re: [PATCH 2/5] dt-bindings: net: add schema for NXP S32CC
 dwmac glue driver

Hi Andrew,

> > > Here I just focus on GMAC since there are other LAN interfaces that S32
> > > family
> > > uses [e.g. PFE]. According to the public GMACSUBSYS ref manual rev2[1]
> > > provided
> > > on NXP website, theoretically GMAC can run SGMII in 1000Mbps and
> > > 2500Mbps so I
> > > assume that supporting 1000BASE-X could be achievable. I'm not sure if
> any
> > > S32
> > > board variant might have SFP ports but RJ-45 [1000BASE-T] should be the
> > > major
> > > type used on S32G-EVB and S32G-RDB2.
> > >
> > > @NXP, please feel free to correct me if anything wrong.
> > >
> >
> > NXP eval boards (EVB or RDB) have also 2.5G PHYs, so together with SerDes
> > driver we support 100M/1G/2.5G on such copper PHYs.
> 
> Hi Jan
> 
> Does the SERDES clock need to change when going between 1000BaseX and
> 2500BaseX?
> 
> If so, it sounds like Linux not having control of that clock is going
> to limit what can be supported.

No, the SerDes clock remains the same, the change is done internally, without
any necessity of clock change intervention by GMAC driver.

/Jan

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