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Message-ID: <20221110102834.8946-1-yunfei.dong@mediatek.com>
Date: Thu, 10 Nov 2022 18:28:32 +0800
From: Yunfei Dong <yunfei.dong@...iatek.com>
To: Yunfei Dong <yunfei.dong@...iatek.com>,
Rob Herring <robh@...nel.org>,
Chen-Yu Tsai <wenst@...omium.org>,
Hans Verkuil <hverkuil-cisco@...all.nl>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>,
Benjamin Gaignard <benjamin.gaignard@...labora.com>,
Tiffany Lin <tiffany.lin@...iatek.com>
CC: Mauro Carvalho Chehab <mchehab@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>,
Hsin-Yi Wang <hsinyi@...omium.org>,
Daniel Vetter <daniel@...ll.ch>,
Steve Cho <stevecho@...omium.org>,
<linux-media@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-mediatek@...ts.infradead.org>,
<Project_Global_Chrome_Upstream_Group@...iatek.com>
Subject: [PATCH v2,1/3] media: dt-bindings: media: mediatek: vcodec: Fix clock num not correctly
mt8195 and mt8192 have different clock numbers, can't write 'clocks' and
'clock-names' with const value.
Move 'assigned-clocks' and 'assigned-clock-parents' to parent node.
Signed-off-by: Yunfei Dong <yunfei.dong@...iatek.com>
---
.../media/mediatek,vcodec-subdev-decoder.yaml | 119 +++++++++++-------
1 file changed, 72 insertions(+), 47 deletions(-)
diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
index c4f20acdc1f8..794012853834 100644
--- a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
@@ -89,23 +89,33 @@ properties:
ranges: true
+ clocks:
+ minItems: 1
+ maxItems: 5
+
+ clock-names:
+ minItems: 1
+ maxItems: 5
+
+ assigned-clocks:
+ maxItems: 1
+
+ assigned-clock-parents:
+ maxItems: 1
+
# Required child node:
patternProperties:
- '^vcodec-lat@[0-9a-f]+$':
+ '^vcodec-lat-soc@[0-9a-f]+$':
type: object
properties:
compatible:
enum:
- - mediatek,mtk-vcodec-lat
- mediatek,mtk-vcodec-lat-soc
reg:
maxItems: 1
- interrupts:
- maxItems: 1
-
iommus:
minItems: 1
maxItems: 32
@@ -114,22 +124,55 @@ patternProperties:
Refer to bindings/iommu/mediatek,iommu.yaml.
clocks:
+ minItems: 1
maxItems: 5
clock-names:
- items:
- - const: sel
- - const: soc-vdec
- - const: soc-lat
- - const: vdec
- - const: top
+ minItems: 1
+ maxItems: 5
- assigned-clocks:
+ power-domains:
maxItems: 1
- assigned-clock-parents:
+ required:
+ - compatible
+ - reg
+ - iommus
+ - clocks
+ - clock-names
+ - power-domains
+
+ additionalProperties: false
+
+ '^vcodec-lat@[0-9a-f]+$':
+ type: object
+
+ properties:
+ compatible:
+ enum:
+ - mediatek,mtk-vcodec-lat
+
+ reg:
+ maxItems: 1
+
+ interrupts:
maxItems: 1
+ iommus:
+ minItems: 1
+ maxItems: 32
+ description: |
+ List of the hardware port in respective IOMMU block for current Socs.
+ Refer to bindings/iommu/mediatek,iommu.yaml.
+
+ clocks:
+ minItems: 1
+ maxItems: 5
+
+ clock-names:
+ minItems: 1
+ maxItems: 5
+
power-domains:
maxItems: 1
@@ -139,8 +182,6 @@ patternProperties:
- iommus
- clocks
- clock-names
- - assigned-clocks
- - assigned-clock-parents
- power-domains
additionalProperties: false
@@ -166,15 +207,12 @@ patternProperties:
Refer to bindings/iommu/mediatek,iommu.yaml.
clocks:
+ minItems: 1
maxItems: 5
clock-names:
- items:
- - const: sel
- - const: soc-vdec
- - const: soc-lat
- - const: vdec
- - const: top
+ minItems: 1
+ maxItems: 5
assigned-clocks:
maxItems: 1
@@ -188,12 +226,9 @@ patternProperties:
required:
- compatible
- reg
- - interrupts
- iommus
- clocks
- clock-names
- - assigned-clocks
- - assigned-clock-parents
- power-domains
additionalProperties: false
@@ -205,17 +240,10 @@ required:
- mediatek,scp
- dma-ranges
- ranges
-
-if:
- properties:
- compatible:
- contains:
- enum:
- - mediatek,mtk-vcodec-lat
-
-then:
- required:
- - interrupts
+ - clocks
+ - clock-names
+ - assigned-clocks
+ - assigned-clock-parents
additionalProperties: false
@@ -241,6 +269,11 @@ examples:
#size-cells = <2>;
ranges = <0 0 0 0x16000000 0 0x40000>;
reg = <0 0x16000000 0 0x1000>; /* VDEC_SYS */
+ clocks = <&topckgen CLK_TOP_VDEC_SEL>,
+ <&topckgen CLK_TOP_MAINPLL_D4>;
+ clock-names = "sel", "top";
+ assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
vcodec-lat@...00 {
compatible = "mediatek,mtk-vcodec-lat";
reg = <0 0x10000 0 0x800>;
@@ -253,14 +286,10 @@ examples:
<&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
<&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
<&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
- clocks = <&topckgen CLK_TOP_VDEC_SEL>,
- <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
+ clocks = <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
<&vdecsys_soc CLK_VDEC_SOC_LAT>,
- <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
- <&topckgen CLK_TOP_MAINPLL_D4>;
+ <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
- assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
- assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
};
@@ -279,14 +308,10 @@ examples:
<&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
<&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
<&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
- clocks = <&topckgen CLK_TOP_VDEC_SEL>,
- <&vdecsys CLK_VDEC_VDEC>,
+ clocks = <&vdecsys CLK_VDEC_VDEC>,
<&vdecsys CLK_VDEC_LAT>,
- <&vdecsys CLK_VDEC_LARB1>,
- <&topckgen CLK_TOP_MAINPLL_D4>;
+ <&vdecsys CLK_VDEC_LARB1>;
clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
- assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
- assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
};
};
--
2.18.0
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