| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <13e37836-b21c-662b-89b5-518fb091c612@huawei.com>
Date: Thu, 10 Nov 2022 20:08:11 +0800
From: Yicong Yang <yangyicong@...wei.com>
To: Junhao He <hejunhao3@...wei.com>, <mathieu.poirier@...aro.org>,
<suzuki.poulose@....com>, <mike.leach@...aro.org>,
<leo.yan@...aro.org>, <jonathan.cameron@...wei.com>,
<john.garry@...wei.com>
CC: <yangyicong@...ilicon.com>, <coresight@...ts.linaro.org>,
<linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>, <lpieralisi@...nel.org>,
<linuxarm@...wei.com>, <liuqi115@...wei.com>,
<f.fangjian@...wei.com>, <prime.zeng@...ilicon.com>
Subject: Re: [PATCH v12 2/2] Documentation: Add document for UltraSoc SMB
drivers
On 2022/11/9 21:50, Junhao He wrote:
> From: Qi Liu <liuqi115@...wei.com>
>
> This patch bring in documentation for UltraSoc SMB drivers.
> It simply describes the device, sysfs interface and the
> firmware bindings.
>
> Signed-off-by: Qi Liu <liuqi115@...wei.com>
> Signed-off-by: Junhao He <hejunhao3@...wei.com>
> ---
> .../sysfs-bus-coresight-devices-ultra_smb | 31 +++++++
> .../trace/coresight/ultrasoc-smb.rst | 80 +++++++++++++++++++
> 2 files changed, 111 insertions(+)
> create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-ultra_smb
> create mode 100644 Documentation/trace/coresight/ultrasoc-smb.rst
>
> diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-ultra_smb b/Documentation/ABI/testing/sysfs-bus-coresight-devices-ultra_smb
> new file mode 100644
> index 000000000000..deaefd508105
> --- /dev/null
> +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-ultra_smb
> @@ -0,0 +1,31 @@
> +What: /sys/bus/coresight/devices/ultra_smb<N>/enable_sink
> +Date: November 2022
> +KernelVersion: 6.2
> +Contact: Junhao He <hejunhao3@...wei.com>
> +Description: (RW) Add/remove a SMB device from a trace path. There can be
> + multiple sources for a single SMB device.
> +
> +What: /sys/bus/coresight/devices/ultra_smb<N>/mgmt/buf_size
> +Date: November 2022
> +KernelVersion: 6.2
> +Contact: Junhao He <hejunhao3@...wei.com>
> +Description: (Read) Shows the buffer size of each UltraSoc SMB device.
> +
> +What: /sys/bus/coresight/devices/ultra_smb<N>/mgmt/buf_status
> +Date: November 2022
> +KernelVersion: 6.2
> +Contact: Junhao He <hejunhao3@...wei.com>
> +Description: (Read) Shows the value held by UltraSoc SMB status register.
> + BIT(0) is zero means buffer is empty.
> +
> +What: /sys/bus/coresight/devices/ultra_smb<N>/mgmt/read_pos
> +Date: November 2022
> +KernelVersion: 6.2
> +Contact: Junhao He <hejunhao3@...wei.com>
> +Description: (Read) Shows the value held by UltraSoc SMB Read Pointer register.
> +
> +What: /sys/bus/coresight/devices/ultra_smb<N>/mgmt/write_pos
> +Date: November 2022
> +KernelVersion: 6.2
> +Contact: Junhao He <hejunhao3@...wei.com>
> +Description: (Read) Shows the value held by UltraSoc SMB Write Pointer register.
> diff --git a/Documentation/trace/coresight/ultrasoc-smb.rst b/Documentation/trace/coresight/ultrasoc-smb.rst
> new file mode 100644
> index 000000000000..6d28ef0f6c88
> --- /dev/null
> +++ b/Documentation/trace/coresight/ultrasoc-smb.rst
> @@ -0,0 +1,80 @@
> +.. SPDX-License-Identifier: GPL-2.0
> +
> +======================================
> +UltraSoc - HW Assisted Tracing on SoC
> +======================================
> + :Author: Qi Liu <liuqi115@...wei.com>
> + :Date: March 2022
> +
> +Introduction
> +------------
> +
> +UltraSoc SMB is a per SCCL(Super CPU Cluster) hardware, and it provides a
> +way to buffer and store CPU trace messages in a region of shared system
> +memory. SMB is plugged as a coresight sink device and the corresponding
> +trace generators (ETM) are plugged in as source devices.
> +
> +Sysfs files and directories
> +---------------------------
> +
> +The SMB devices appear on the existing coresight bus alongside the other
> +coresight devices::
> +
> + $# ls /sys/bus/coresight/devices/
> + ultra_smb0 ultra_smb1 ultra_smb2 ultra_smb3
> +
> +The ``ultra_smb<N>`` named SMB associated with SCCL.::
> +
> + $# ls /sys/bus/coresight/devices/ultra_smb0
> + enable_sink mgmt
> + $# ls /sys/bus/coresight/devices/ultra_smb0/mgmt
> + buf_size buf_status read_pos write_pos
> +
> +*Key file items are:-*
> + * ``read_pos``: Shows the value held by UltraSoc SMB Read Pointer register.
> + * ``write_pos``: Shows the value held by UltraSoc SMB Write Pointer register.
> + * ``buf_status``: Shows the value held by UltraSoc SMB status register.
> + BIT(0) is zero means buffer is empty.
> + * ``buf_size``: Shows the buffer size of each UltraSoc SMB device.
> +
> +Firmware Bindings
> +---------------------------
> +
> +SMB device is only supported with ACPI, and ACPI binding of SMB device
> +describes SMB device indentifier, resource information and graph structure.
> +
> +SMB is identified by ACPI HID "HISI03A1", resource of device is declared using
> +the _CRS method. Each SMB must present two base address, the first one is the
> +configuration base address of SMB device, the second one is the base address of
> +shared system memory.
> +
> +examples::
> +
> + Device(USMB) { \
> + Name(_HID, "HISI03A1") \
> + Name(_CRS, ResourceTemplate() { \
> + MEM_RESRC(0x95100000, 0x951FFFFF, 0x100000) \
> + MEM_RESRC(0x50000000, 0x53FFFFFF, 0x4000000) \
I cannot find MEM_RESRC in ACPI Spec 6.4, any references? If it's a self defined macro just expand it here.
btw, you need to cc linux-doc@...r.kernel.org.
Thanks.
> + }) \
> + Name(_DSD, Package() { \
> + ToUUID("ab02a46b-74c7-45a2-bd68-f7d344ef2153"), \
> + /* Use CoreSight Graph ACPI bindings to describe connections topology */
> + Package() { \
> + 0, \
> + 1, \
> + Package() { \
> + 1, \
> + ToUUID("3ecbc8b6-1d0e-4fb3-8107-e627f805c6cd"), \
> + 8, \
> + Package() {0x8, 0, \_SB.S00.SL11.CL28.F008, 0}, \
> + Package() {0x9, 0, \_SB.S00.SL11.CL29.F009, 0}, \
> + Package() {0xa, 0, \_SB.S00.SL11.CL2A.F010, 0}, \
> + Package() {0xb, 0, \_SB.S00.SL11.CL2B.F011, 0}, \
> + Package() {0xc, 0, \_SB.S00.SL11.CL2C.F012, 0}, \
> + Package() {0xd, 0, \_SB.S00.SL11.CL2D.F013, 0}, \
> + Package() {0xe, 0, \_SB.S00.SL11.CL2E.F014, 0}, \
> + Package() {0xf, 0, \_SB.S00.SL11.CL2F.F015, 0}, \
> + } \
> + } \
> + }) \
> + }
>
Powered by blists - more mailing lists