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Message-Id: <20221110163845.42309-5-frattaroli.nicolas@gmail.com>
Date: Thu, 10 Nov 2022 17:38:45 +0100
From: Nicolas Frattaroli <frattaroli.nicolas@...il.com>
To: Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Heiko Stuebner <heiko@...ech.de>
Cc: Nicolas Frattaroli <frattaroli.nicolas@...il.com>,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: [PATCH 4/4] arm64: dts: rockchip: Enable PCIe 2 on SOQuartz CM4IO
This patch enables the PCIe2 on the CM4IO board when paired with
a SOQuartz CM4 System-on-Module board. combphy2 also needs to be
enabled in this case to make the PHY work for this.
Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@...il.com>
---
arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts | 10 ++++++++++
arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi | 12 ++++++++++++
2 files changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts
index e00568a6be5c..4cf60be267ed 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts
@@ -30,6 +30,11 @@ vcc_5v: vcc-5v-regulator {
};
};
+/* phy for pcie */
+&combphy2 {
+ status = "okay";
+};
+
&gmac1 {
status = "okay";
};
@@ -105,6 +110,11 @@ &led_work {
status = "okay";
};
+&pcie2x1 {
+ vpcie3v3-supply = <&vcc_3v3>;
+ status = "okay";
+};
+
&rgmii_phy1 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi
index 1b975822effa..294354e95336 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi
@@ -487,6 +487,12 @@ rgmii_phy1: ethernet-phy@0 {
};
};
+&pcie2x1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_reset_h>;
+ reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
+};
+
&pinctrl {
bt {
bt_enable_h: bt-enable-h {
@@ -512,6 +518,12 @@ diy_led_enable_h: diy-led-enable-h {
};
};
+ pcie {
+ pcie_reset_h: pcie-reset-h {
+ rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
--
2.38.1
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