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Date: Thu, 10 Nov 2022 19:25:12 -0800
From: Bjorn Andersson <quic_bjorande@...cinc.com>
To: Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...ainline.org>,
Sibi Sankar <quic_sibis@...cinc.com>
CC: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
Georgi Djakov <djakov@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Mike Tipton <quic_mdtipton@...cinc.com>,
Johan Hovold <johan+linaro@...nel.org>,
<linux-arm-msm@...r.kernel.org>, <linux-pm@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: [PATCH v2 07/10] arm64: dts: qcom: sc8280xp: Add epss_l3 node
Add a device node for the EPSS L3 frequency domain.
Signed-off-by: Bjorn Andersson <quic_bjorande@...cinc.com>
Tested-by: Steev Klimaszewski <steev@...i.org>
---
Changes since v1:
- None
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 6bc12e507d21..0e80cdcf6bcf 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -1782,6 +1782,16 @@
};
};
+ epss_l3: interconnect@...90000 {
+ compatible = "qcom,sc8280xp-epss-l3", "qcom,epss-l3";
+ reg = <0 0x18590000 0 0x1000>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
+ clock-names = "xo", "alternate";
+
+ #interconnect-cells = <1>;
+ };
+
cpufreq_hw: cpufreq@...91000 {
compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss";
reg = <0 0x18591000 0 0x1000>,
--
2.17.1
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