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Message-ID: <ace91d8b-9a14-5569-7c59-344e9751fa96@linaro.org>
Date: Sat, 12 Nov 2022 14:43:03 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Johan Hovold <johan+linaro@...nel.org>,
Vinod Koul <vkoul@...nel.org>
Cc: Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
linux-arm-msm@...r.kernel.org, linux-phy@...ts.infradead.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 02/14] dt-bindings: phy: qcom,qmp-usb3-dp: fix sc8280xp
bindings
On 11/11/2022 12:24, Johan Hovold wrote:
> The current QMP USB3-DP PHY bindings are based on the original MSM8996
> binding which provided multiple PHYs per IP block and these in turn were
> described by child nodes.
>
> The QMP USB3-DP PHY block provides a single multi-protocol PHY and even
> if some resources are only used by either the USB or DP part of the
> device there is no real benefit in describing these resources in child
> nodes.
>
> The original MSM8996 binding also ended up describing the individual
> register blocks as belonging to either the wrapper node or the PHY child
> nodes.
>
> This is an unnecessary level of detail which has lead to problems when
> later IP blocks using different register layouts have been forced to fit
> the original mould rather than updating the binding. The bindings are
> arguable also incomplete as they only the describe register blocks used
> by the current Linux drivers (e.g. does not include the PCS LANE
> registers).
>
> This is specifically true for later USB4-USB3-DP QMP PHYs where the TX
> registers are used by both the USB3 and DP parts of the PHY (and where
> the USB4 part of the PHY was not covered by the binding at all). Notably
> there are also no DP "RX" (sic) registers as described by the current
> bindings and the DP "PCS" region is really a set of DP_PHY registers.
>
> Add a new binding for the USB4-USB3-DP QMP PHYs found on SC8280XP which
> further bindings can be based on.
>
> Note that the binding uses a PHY type index to access either the USB3 or
> DP part of the PHY and that this can later be used also for the USB4
> part if needed.
>
> Similarly, the clock inputs and outputs can later be extended to support
> USB4.
>
> Also note that the current binding is simply removed instead of being
> deprecated as it was only recently merged and would not allow for
> supporting DP mode.
>
> Signed-off-by: Johan Hovold <johan+linaro@...nel.org>
> ---
> .../phy/qcom,sc7180-qmp-usb3-dp-phy.yaml | 12 --
> .../phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml | 111 ++++++++++++++++++
> 2 files changed, 111 insertions(+), 12 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/qcom,sc7180-qmp-usb3-dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc7180-qmp-usb3-dp-phy.yaml
> index 50b1fce530d5..2f4a419197a8 100644
> --- a/Documentation/devicetree/bindings/phy/qcom,sc7180-qmp-usb3-dp-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/qcom,sc7180-qmp-usb3-dp-phy.yaml
> @@ -23,7 +23,6 @@ properties:
> - qcom,sc7180-qmp-usb3-dp-phy
> - qcom,sc7280-qmp-usb3-dp-phy
> - qcom,sc8180x-qmp-usb3-dp-phy
> - - qcom,sc8280xp-qmp-usb43dp-phy
> - qcom,sdm845-qmp-usb3-dp-phy
> - qcom,sm8250-qmp-usb3-dp-phy
> reg:
> @@ -169,17 +168,6 @@ required:
>
> additionalProperties: false
>
> -allOf:
> - - if:
> - properties:
> - compatible:
> - contains:
> - enum:
> - - qcom,sc8280xp-qmp-usb43dp-phy
> - then:
> - required:
> - - power-domains
> -
> examples:
> - |
> #include <dt-bindings/clock/qcom,gcc-sdm845.h>
> diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
> new file mode 100644
> index 000000000000..bd04150acee4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
> @@ -0,0 +1,111 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm QMP USB4-USB3-DP PHY controller (SC8280XP)
> +
> +maintainers:
> + - Vinod Koul <vkoul@...nel.org>
> +
> +description:
> + The QMP PHY controller supports physical layer functionality for a number of
> + controllers on Qualcomm chipsets, such as, PCIe, UFS and USB.
> +
> + See also:
> + - include/dt-bindings/dt-bindings/phy/phy.h
> +
> +properties:
> + compatible:
> + enum:
> + - qcom,sc8280xp-qmp-usb43dp-phy
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 4
> +
> + clock-names:
> + items:
> + - const: aux
> + - const: ref
> + - const: com_aux
> + - const: usb3_pipe
> +
> + power-domains:
> + maxItems: 1
> +
> + resets:
> + maxItems: 2
> +
> + reset-names:
> + items:
> + - const: phy
> + - const: common
> +
> + vdda-phy-supply: true
> +
> + vdda-pll-supply: true
> +
> + "#clock-cells":
> + const: 1
> +
> + clock-output-names:
> + items:
> + - const: usb3_pipe
> + - const: dp_link
> + - const: dp_vco_div
> +
> + "#phy-cells":
> + const: 1
> + description: |
> + PHY index
> + - PHY_TYPE_USB3
> + - PHY_TYPE_DP
I'm stepping on Rob's and Krzysztof's ground here, but it might be more
logical and future proof to use indices instead of phy types.
Just for my understanding, would USB4 support add another qserdes+tx/rx
construct or would it be the same USB3 register space?
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - power-domains
> + - resets
> + - reset-names
> + - vdda-phy-supply
> + - vdda-pll-supply
> + - "#clock-cells"
> + - clock-output-names
> + - "#phy-cells"
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
> +
> + phy@...b000 {
> + compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
> + reg = <0x088eb000 0x4000>;
> +
> + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
> + <&gcc GCC_USB4_EUD_CLKREF_CLK>,
> + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
> + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
> + clock-names = "aux", "ref", "com_aux", "usb3_pipe";
> +
> + power-domains = <&gcc USB30_PRIM_GDSC>;
> +
> + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
> + <&gcc GCC_USB4_DP_PHY_PRIM_BCR>;
> + reset-names = "phy", "common";
> +
> + vdda-phy-supply = <&vreg_l9d>;
> + vdda-pll-supply = <&vreg_l4d>;
> +
> + #clock-cells = <1>;
> + clock-output-names = "usb3_pipe", "dp_link", "dp_vco_div";
> +
> + #phy-cells = <1>;
> + };
--
With best wishes
Dmitry
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