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Message-ID: <OS0PR01MB59224DF03590185EFD5AF91386059@OS0PR01MB5922.jpnprd01.prod.outlook.com>
Date: Mon, 14 Nov 2022 19:10:41 +0000
From: Biju Das <biju.das.jz@...renesas.com>
To: Geert Uytterhoeven <geert@...ux-m68k.org>
CC: Prabhakar <prabhakar.csengg@...il.com>,
Geert Uytterhoeven <geert+renesas@...der.be>,
Wim Van Sebroeck <wim@...ux-watchdog.org>,
Guenter Roeck <linux@...ck-us.net>,
Philipp Zabel <p.zabel@...gutronix.de>,
"linux-watchdog@...r.kernel.org" <linux-watchdog@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-renesas-soc@...r.kernel.org"
<linux-renesas-soc@...r.kernel.org>,
Fabrizio Castro <fabrizio.castro.jz@...esas.com>,
Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: RE: [PATCH] watchdog: rzg2l_wdt: Issue a reset before we put the PM
clocks
> -----Original Message-----
> From: Geert Uytterhoeven <geert@...ux-m68k.org>
> Sent: 14 November 2022 19:04
> To: Biju Das <biju.das.jz@...renesas.com>
> Cc: Prabhakar <prabhakar.csengg@...il.com>; Geert Uytterhoeven
> <geert+renesas@...der.be>; Wim Van Sebroeck <wim@...ux-watchdog.org>; Guenter
> Roeck <linux@...ck-us.net>; Philipp Zabel <p.zabel@...gutronix.de>; linux-
> watchdog@...r.kernel.org; linux-kernel@...r.kernel.org; linux-renesas-
> soc@...r.kernel.org; Fabrizio Castro <fabrizio.castro.jz@...esas.com>;
> Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@...renesas.com>
> Subject: Re: [PATCH] watchdog: rzg2l_wdt: Issue a reset before we put the PM
> clocks
>
> Hi Biju,
>
> On Mon, Nov 14, 2022 at 7:42 PM Biju Das <biju.das.jz@...renesas.com> wrote:
> > > -----Original Message-----
> > > From: Prabhakar <prabhakar.csengg@...il.com>
> > > Sent: 14 November 2022 18:09
> > > To: Geert Uytterhoeven <geert+renesas@...der.be>; Wim Van Sebroeck
> > > <wim@...ux-watchdog.org>; Guenter Roeck <linux@...ck-us.net>;
> > > Philipp Zabel <p.zabel@...gutronix.de>;
> > > linux-watchdog@...r.kernel.org
> > > Cc: linux-kernel@...r.kernel.org; linux-renesas-soc@...r.kernel.org;
> > > Prabhakar <prabhakar.csengg@...il.com>; Biju Das
> > > <biju.das.jz@...renesas.com>; Fabrizio Castro
> > > <fabrizio.castro.jz@...esas.com>; Prabhakar Mahadev Lad
> > > <prabhakar.mahadev- lad.rj@...renesas.com>
> > > Subject: [PATCH] watchdog: rzg2l_wdt: Issue a reset before we put
> > > the PM clocks
> > >
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> > >
> > > On RZ/Five SoC it was observed that setting timeout (to say 1 sec)
> > > wouldn't reset the system. To fix this we make sure we issue a reset
> > > before putting the PM clocks to make sure the registers have been
> cleared.
> > >
> > > While at it re-used rzg2l_wdt_stop() in rzg2l_wdt_set_timeout() as
> > > we were calling the same functions here.
> > >
> > > Signed-off-by: Lad Prabhakar
> > > <prabhakar.mahadev-lad.rj@...renesas.com>
> > > ---
> > > Note,
> > > - This patch has been tested on RZ/G2L, RZ/V2M and RZ/Five.
> > > - My initial investigation showed adding the delay after
> > > pm_runtime_get_sync()
> > > also fixed this issue.
> > > - Do I need add the fixes tag ? what should be the operation PUT-
> > > >RESET/RESET->PUT?
> >
> > It looks like timing issue, None of the previous devices are affected by
> this.
>
> To me it looks like the device must be clocked for the reset signal to be
> propagated?
Yep, provide clk supply for a device, then apply reset.
Cheers,
Biju
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