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Message-ID: <fa8de189-8477-462b-e55a-a3046bbdbb36@arm.com>
Date: Mon, 14 Nov 2022 10:03:09 +0100
From: Pierre Gondois <pierre.gondois@....com>
To: Shawn Guo <shawnguo@...nel.org>, Chester Lin <clin@...e.com>
Cc: linux-kernel@...r.kernel.org, Rob.Herring@....com,
Li Yang <leoyang.li@....com>, Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
Fabio Estevam <festevam@...il.com>,
NXP Linux Team <linux-imx@....com>,
Andreas Färber <afaerber@...e.de>,
Matthias Brugger <mbrugger@...e.com>,
NXP S32 Linux Team <s32@....com>,
Peng Fan <peng.fan@....com>, Jacky Bai <ping.bai@....com>,
Sudeep Holla <sudeep.holla@....com>,
linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org
Subject: Re: [PATCH 07/20] arm64: dts: Update cache properties for freescale
On 11/11/22 05:57, Shawn Guo wrote:
> On Fri, Nov 11, 2022 at 12:49:08PM +0800, Chester Lin wrote:
>> Hi Shawn,
>>
>> On Fri, Nov 11, 2022 at 10:55:53AM +0800, Shawn Guo wrote:
>>> On Mon, Oct 31, 2022 at 10:19:51AM +0100, Pierre Gondois wrote:
>>>> The DeviceTree Specification v0.3 specifies that the cache node
>>>> 'compatible' and 'cache-level' properties are 'required'. Cf.
>>>> s3.8 Multi-level and Shared Cache Nodes
>>>>
>>>> The recently added init_of_cache_level() function checks
>>>> these properties. Add them if missing.
>>>>
>>>> Signed-off-by: Pierre Gondois <pierre.gondois@....com>
>>>
>>> Looks good to me. Should I pick it up on IMX tree, or it needs to go as
>>> part of the series (via other tree)?
>>>
>>> Shawn
>>>
>>
>> The change for s32g2 looks good to me. I would be grateful if you could pick
>> this patch to the IMX tree. Thanks!
>>
>> Reviewed-by: Chester Lin <clin@...e.com>
>
> Ok, I will wait a confirmation from Pierre that the intention is indeed
> for platform maintainer to pick up individual patch.
>
> Shawn
Hello Shawn, Chester,
Yes please pick the patch individually,
Regards,
Pierre
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