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Date:   Mon, 14 Nov 2022 12:24:16 +0200
From:   Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
To:     Rahul Tanwar <rtanwar@...linear.com>
Cc:     "bigeasy@...utronix.de" <bigeasy@...utronix.de>,
        "robh@...nel.org" <robh@...nel.org>,
        "tglx@...utronix.de" <tglx@...utronix.de>,
        "mingo@...hat.com" <mingo@...hat.com>,
        "bp@...en8.de" <bp@...en8.de>, "x86@...nel.org" <x86@...nel.org>,
        "hpa@...or.com" <hpa@...or.com>,
        "dave.hansen@...ux.intel.com" <dave.hansen@...ux.intel.com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        linux-lgm-soc <linux-lgm-soc@...linear.com>
Subject: Re: [PATCH RESEND 1/1] x86/of: Add support for boot time interrupt
 mode config

On Mon, Nov 14, 2022 at 10:00:02AM +0000, Rahul Tanwar wrote:
> On 14/11/2022 5:45 pm, Andy Shevchenko wrote:
> > On Mon, Nov 14, 2022 at 05:20:06PM +0800, Rahul Tanwar wrote:

...

> >> +     if (of_property_read_bool(dn, "intel,no-imcr")) {
> > 
> > I can't find this property in the Documentation/devicetree/bindings.
> > 
> > Moreover, I prefer to see positive one, something like:
> > 
> >          intel,virtual-wire-bla-bla-bla
> > 
> > Please consult with DT people on how properly name it.
> 
> 
> Yes, agree. Need to add it in bindings doc after finalizing the property 
> name. I chose "intel,no-imcr" to have a direct correlation with the MPS
> spec defined data field for the same purpose.

The problems with it are:
- it's negative
- it's too cryptic to one who doesn't know area well enough

> It reads below bit in 
> mpparse code to detect PIC mode or virtual wire mode.
> 
> Bit 7: IMCRP. When the IMCR presence bit is set, the IMCR is present and 
> PIC Mode is implemented; otherwise, Virtual Wire Mode is implemented.
> 
> Please refer [1]
> 
> [1] https://www.manualslib.com/manual/77733/Intel 
> Multiprocessor.html?page=40#manual

This is good reference for DT people to suggest you a better name.

-- 
With Best Regards,
Andy Shevchenko


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