lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Tue, 15 Nov 2022 14:24:24 -0300
From:   Fabio Estevam <festevam@...il.com>
To:     Frieder Schrempf <frieder@...s.de>
Cc:     David Jander <david@...tonic.nl>,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        linux-spi@...r.kernel.org, Marc Kleine-Budde <mkl@...gutronix.de>,
        Mark Brown <broonie@...nel.org>,
        Sascha Hauer <s.hauer@...gutronix.de>,
        Shawn Guo <shawnguo@...nel.org>,
        Frieder Schrempf <frieder.schrempf@...tron.de>,
        Marek Vasut <marex@...x.de>, stable@...r.kernel.org,
        Baruch Siach <baruch.siach@...lu.com>,
        Minghao Chi <chi.minghao@....com.cn>,
        NXP Linux Team <linux-imx@....com>,
        Pengutronix Kernel Team <kernel@...gutronix.de>
Subject: Re: [PATCH v2] spi: spi-imx: Fix spi_bus_clk if requested clock is
 higher than input clock

On Tue, Nov 15, 2022 at 1:27 PM Frieder Schrempf <frieder@...s.de> wrote:
>
> From: Frieder Schrempf <frieder.schrempf@...tron.de>
>
> In case the requested bus clock is higher than the input clock, the correct
> dividers (pre = 0, post = 0) are returned from mx51_ecspi_clkdiv(), but
> *fres is left uninitialized and therefore contains an arbitrary value.
>
> This causes trouble for the recently introduced PIO polling feature as the
> value in spi_imx->spi_bus_clk is used there to calculate for which
> transfers to enable PIO polling.
>
> Fix this by setting *fres even if no clock dividers are in use.
>
> This issue was observed on Kontron BL i.MX8MM with an SPI peripheral clock set
> to 50 MHz by default and a requested SPI bus clock of 80 MHz for the SPI NOR
> flash.
>
> With the fix applied the debug message from mx51_ecspi_clkdiv() now prints the
> following:
>
> spi_imx 30820000.spi: mx51_ecspi_clkdiv: fin: 50000000, fspi: 50000000,
> post: 0, pre: 0
>
> Fixes: 07e759387788 ("spi: spi-imx: add PIO polling support")
> Cc: Marc Kleine-Budde <mkl@...gutronix.de>
> Cc: David Jander <david@...tonic.nl>
> Cc: Fabio Estevam <festevam@...il.com>
> Cc: Mark Brown <broonie@...nel.org>
> Cc: Marek Vasut <marex@...x.de>
> Cc: stable@...r.kernel.org
> Signed-off-by: Frieder Schrempf <frieder.schrempf@...tron.de>

Thanks for the fix:

Tested-by: Fabio Estevam <festevam@...il.com>

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ