lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <0D3A45FE-5367-40CD-A035-37F6EE98B25E@vmware.com>
Date:   Tue, 15 Nov 2022 23:38:32 +0000
From:   Nadav Amit <namit@...are.com>
To:     Yicong Yang <yangyicong@...wei.com>
CC:     Andrew Morton <akpm@...ux-foundation.org>,
        Linux-MM <linux-mm@...ck.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>, X86 ML <x86@...nel.org>,
        Catalin Marinas <catalin.marinas@....com>,
        Will Deacon <will@...nel.org>,
        Anshuman Khandual <anshuman.khandual@....com>,
        "linux-doc@...r.kernel.org" <linux-doc@...r.kernel.org>,
        Jonathan Corbet <corbet@....net>,
        Peter Zijlstra <peterz@...radead.org>,
        Arnd Bergmann <arnd@...db.de>,
        "punit.agrawal@...edance.com" <punit.agrawal@...edance.com>,
        kernel list <linux-kernel@...r.kernel.org>,
        "darren@...amperecomputing.com" <darren@...amperecomputing.com>,
        "yangyicong@...ilicon.com" <yangyicong@...ilicon.com>,
        "huzhanyuan@...o.com" <huzhanyuan@...o.com>,
        "lipeifeng@...o.com" <lipeifeng@...o.com>,
        "zhangshiming@...o.com" <zhangshiming@...o.com>,
        "guojian@...o.com" <guojian@...o.com>,
        "realmz6@...il.com" <realmz6@...il.com>,
        "linux-mips@...r.kernel.org" <linux-mips@...r.kernel.org>,
        "openrisc@...ts.librecores.org" <openrisc@...ts.librecores.org>,
        linuxppc-dev <linuxppc-dev@...ts.ozlabs.org>,
        "linux-riscv@...ts.infradead.org" <linux-riscv@...ts.infradead.org>,
        linux-s390 <linux-s390@...r.kernel.org>,
        Barry Song <21cnbao@...il.com>,
        "wangkefeng.wang@...wei.com" <wangkefeng.wang@...wei.com>,
        haoxin <xhao@...ux.alibaba.com>,
        "prime.zeng@...ilicon.com" <prime.zeng@...ilicon.com>,
        Barry Song <v-songbaohua@...o.com>,
        Mel Gorman <mgorman@...e.de>
Subject: Re: [PATCH v6 2/2] arm64: support batched/deferred tlb shootdown
 during page reclamation

On Nov 14, 2022, at 7:14 PM, Yicong Yang <yangyicong@...wei.com> wrote:

> diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h
> index 8a497d902c16..5bd78ae55cd4 100644
> --- a/arch/x86/include/asm/tlbflush.h
> +++ b/arch/x86/include/asm/tlbflush.h
> @@ -264,7 +264,8 @@ static inline u64 inc_mm_tlb_gen(struct mm_struct *mm)
> }
> 
> static inline void arch_tlbbatch_add_mm(struct arch_tlbflush_unmap_batch *batch,
> -					struct mm_struct *mm)
> +					struct mm_struct *mm,
> +					unsigned long uaddr)

Logic-wise it looks fine. I notice the “v6", and it should not be blocking,
but I would note that the name "arch_tlbbatch_add_mm()” does not make much
sense once the function also takes an address.

It could’ve been something like arch_set_tlb_ubc_flush_pending() but that’s
too long. I’m not very good with naming, but the current name is not great.


Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ