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Date:   Tue, 15 Nov 2022 07:46:00 +0100
From:   Andrew Jones <ajones@...tanamicro.com>
To:     Deepak Gupta <debug@...osinc.com>
Cc:     aou@...s.berkeley.edu, jan.kiszka@...mens.com, kbingham@...nel.org,
        linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org,
        palmer@...belt.com, paul.walmsley@...ive.com
Subject: Re: [PATCH v2] scripts/gdb: add lx_current support for riscv

On Mon, Nov 14, 2022 at 05:29:17PM -0800, Deepak Gupta wrote:
> csr_sscratch CSR holds current task_struct address when hart is in user space.
> trap handler on entry spills csr_sscratch into "tp" (x2) register and zeroes out
> csr_sscratch CSR. trap handler on exit reloads "tp" with expected user mode value
> and place current task_struct address again in csr_scratch CSR.
> 
> This patch assumes "tp" is pointing to task_struct. If value in csr_scratch is numerically
> greater than "tp" then it assumes csr_scratch is correct address of current task_struct.
> This logic holds when
>    - hart is in user space, "tp" will be less than csr_scratch.
>    - hart is in kernel space but not in trap handler, "tp" will be more than csr_scratch.
>    - hart is executing trap handler
>            - "tp" is still pointing to user mode but csr_scratch contains ptr to task_struct.
>              numerically higher.
>            - "tp" is now pointing to task_struct but csr_scratch now contains either 0 or numerically
>               smaller value.

When is (csr_scratch != 0 && csr_scratch < tp)? IIUC, it should always be
zero or >= tp.

> 
> Patch also adds new cached type "ulong" in scripts/gdb/linux/utils.py

Please wrap commit message lines at ~74.

> 
> Signed-off-by: Deepak Gupta <debug@...osinc.com>
> ---
>  scripts/gdb/linux/cpus.py  | 15 +++++++++++++++
>  scripts/gdb/linux/utils.py |  5 +++++
>  2 files changed, 20 insertions(+)
> 
> diff --git a/scripts/gdb/linux/cpus.py b/scripts/gdb/linux/cpus.py
> index 15fc4626d236..fd818d7896ce 100644
> --- a/scripts/gdb/linux/cpus.py
> +++ b/scripts/gdb/linux/cpus.py
> @@ -173,6 +173,21 @@ def get_current_task(cpu):
>           else:
>               raise gdb.GdbError("Sorry, obtaining the current task is not allowed "
>                                  "while running in userspace(EL0)")
> +    elif utils.is_target_arch("riscv"):
> +         current_tp = gdb.parse_and_eval("$tp")
> +         scratch_reg = gdb.parse_and_eval("$sscratch")
> +
> +         # by default tp points to current task
> +         current_task = current_tp.cast(task_ptr_type)
> +         
> +         # scratch register is set 0 in trap handler after entering kernel.
> +         # When hart is in user mode, scratch register is pointing to task_struct.
> +         # So when scratch register holds higher value (negative address as ulong is bigger value) than tp,

Please wrap source lines at 100.

> +         # then use scratch register
> +         if (scratch_reg.cast(utils.get_ulong_type()) >  current_tp.cast(utils.get_ulong_type())):
                                                          ^ extra space here

> +             current_task = scratch_reg.cast(task_ptr_type)
> +             
> +         return current_task.dereference()
>      else:
>          raise gdb.GdbError("Sorry, obtaining the current task is not yet "
>                             "supported with this arch")
> diff --git a/scripts/gdb/linux/utils.py b/scripts/gdb/linux/utils.py
> index 1553f68716cc..ddaf3089170d 100644
> --- a/scripts/gdb/linux/utils.py
> +++ b/scripts/gdb/linux/utils.py
> @@ -35,12 +35,17 @@ class CachedType:
>  
>  
>  long_type = CachedType("long")
> +ulong_type = CachedType("ulong")
>  atomic_long_type = CachedType("atomic_long_t")
>  
>  def get_long_type():
>      global long_type
>      return long_type.get_type()
>  
> +def get_ulong_type():
> +    global ulong_type
> +    return ulong_type.get_type()
> +
>  def offset_of(typeobj, field):
>      element = gdb.Value(0).cast(typeobj)
>      return int(str(element[field].address).split()[0], 16)
> -- 
> 2.25.1
>

Besides the line wrapping and the commit message clarification this looks
good to me.

Reviewed-by: Andrew Jones <ajones@...tanamicro.com>

Thanks,
drew

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