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Message-Id: <20221115073603.3425396-4-clabbe@baylibre.com>
Date: Tue, 15 Nov 2022 07:36:03 +0000
From: Corentin Labbe <clabbe@...libre.com>
To: andrew@...n.ch, broonie@...nel.org, calvin.johnson@....nxp.com,
davem@...emloft.net, edumazet@...gle.com, hkallweit1@...il.com,
jernej.skrabec@...il.com, krzysztof.kozlowski+dt@...aro.org,
kuba@...nel.org, lgirdwood@...il.com, linux@...linux.org.uk,
pabeni@...hat.com, robh+dt@...nel.org, samuel@...lland.org,
wens@...e.org
Cc: devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, linux-sunxi@...ts.linux.dev,
netdev@...r.kernel.org, linux-sunxi@...glegroups.com,
Ondřej Jirman <megi@....cz>,
Corentin Labbe <clabbe@...libre.com>
Subject: [PATCH v4 3/3] arm64: dts: allwinner: orange-pi-3: Enable ethernet
From: Ondřej Jirman <megi@....cz>
Orange Pi 3 has two regulators that power the Realtek RTL8211E
PHY. According to the datasheet, both regulators need to be enabled
at the same time, or that "phy-io" should be enabled slightly earlier
than "phy" regulator.
RTL8211E/RTL8211EG datasheet says:
Note 4: 2.5V (or 1.8/1.5V) RGMII power should be risen simultaneously
or slightly earlier than 3.3V power. Rising 2.5V (or 1.8/1.5V) power
later than 3.3V power may lead to errors.
The timing is set in DT via startup-delay-us.
Signed-off-by: Ondrej Jirman <megi@....cz>
Signed-off-by: Corentin Labbe <clabbe@...libre.com>
---
.../dts/allwinner/sun50i-h6-orangepi-3.dts | 38 +++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
index 6fc65e8db220..081b004f26ea 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
@@ -13,6 +13,7 @@ / {
compatible = "xunlong,orangepi-3", "allwinner,sun50i-h6";
aliases {
+ ethernet0 = &emac;
serial0 = &uart0;
serial1 = &uart1;
};
@@ -55,6 +56,15 @@ led-1 {
};
};
+ reg_gmac_2v5: gmac-2v5 {
+ compatible = "regulator-fixed";
+ regulator-name = "gmac-2v5";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ enable-active-high;
+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
+ };
+
reg_vcc5v: vcc5v {
/* board wide 5V supply directly from the DC jack */
compatible = "regulator-fixed";
@@ -113,6 +123,33 @@ &ehci3 {
status = "okay";
};
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ext_rgmii_pins>;
+ phy-mode = "rgmii-id";
+ phy-handle = <&ext_rgmii_phy>;
+ status = "okay";
+};
+
+&mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ /*
+ * The board uses 2.5V RGMII signalling. Power sequence to enable
+ * the phy is to enable GMAC-2V5 and GMAC-3V (aldo2) power rails
+ * at the same time and to wait 100ms. The driver enables phy-io
+ * first. Delay is achieved with enable-ramp-delay on reg_aldo2.
+ */
+ phy-io-supply = <®_gmac_2v5>;
+ ephy-supply = <®_aldo2>;
+
+ reset-gpios = <&pio 3 14 GPIO_ACTIVE_LOW>; /* PD14 */
+ reset-assert-us = <15000>;
+ reset-deassert-us = <40000>;
+ };
+};
+
&gpu {
mali-supply = <®_dcdcc>;
status = "okay";
@@ -211,6 +248,7 @@ reg_aldo2: aldo2 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc33-audio-tv-ephy-mac";
+ regulator-enable-ramp-delay = <100000>;
};
/* ALDO3 is shorted to CLDO1 */
--
2.37.4
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