linux-kernel - Re: [PATCH v6 2/2] arm64: support batched/deferred tlb shootdown during page reclamation

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Message-ID: <01ffa482-8d59-4cf9-f103-fb39a987873d@arm.com>
Date:   Wed, 16 Nov 2022 08:21:12 +0530
From:   Anshuman Khandual <anshuman.khandual@....com>
To:     Nadav Amit <namit@...are.com>, Yicong Yang <yangyicong@...wei.com>
Cc:     "yangyicong@...ilicon.com" <yangyicong@...ilicon.com>,
        Andrew Morton <akpm@...ux-foundation.org>,
        Linux-MM <linux-mm@...ck.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>, X86 ML <x86@...nel.org>,
        Catalin Marinas <catalin.marinas@....com>,
        Will Deacon <will@...nel.org>,
        "linux-doc@...r.kernel.org" <linux-doc@...r.kernel.org>,
        Jonathan Corbet <corbet@....net>,
        Peter Zijlstra <peterz@...radead.org>,
        Arnd Bergmann <arnd@...db.de>,
        "punit.agrawal@...edance.com" <punit.agrawal@...edance.com>,
        kernel list <linux-kernel@...r.kernel.org>,
        "darren@...amperecomputing.com" <darren@...amperecomputing.com>,
        "huzhanyuan@...o.com" <huzhanyuan@...o.com>,
        "lipeifeng@...o.com" <lipeifeng@...o.com>,
        "zhangshiming@...o.com" <zhangshiming@...o.com>,
        "guojian@...o.com" <guojian@...o.com>,
        "realmz6@...il.com" <realmz6@...il.com>,
        "linux-mips@...r.kernel.org" <linux-mips@...r.kernel.org>,
        "openrisc@...ts.librecores.org" <openrisc@...ts.librecores.org>,
        linuxppc-dev <linuxppc-dev@...ts.ozlabs.org>,
        "linux-riscv@...ts.infradead.org" <linux-riscv@...ts.infradead.org>,
        linux-s390 <linux-s390@...r.kernel.org>,
        Barry Song <21cnbao@...il.com>,
        "wangkefeng.wang@...wei.com" <wangkefeng.wang@...wei.com>,
        haoxin <xhao@...ux.alibaba.com>,
        "prime.zeng@...ilicon.com" <prime.zeng@...ilicon.com>,
        Barry Song <v-songbaohua@...o.com>,
        Mel Gorman <mgorman@...e.de>
Subject: Re: [PATCH v6 2/2] arm64: support batched/deferred tlb shootdown
 during page reclamation



On 11/16/22 07:26, Nadav Amit wrote:
> On Nov 15, 2022, at 5:50 PM, Yicong Yang <yangyicong@...wei.com> wrote:
> 
>> !! External Email
>>
>> On 2022/11/16 7:38, Nadav Amit wrote:
>>> On Nov 14, 2022, at 7:14 PM, Yicong Yang <yangyicong@...wei.com> wrote:
>>>
>>>> diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h
>>>> index 8a497d902c16..5bd78ae55cd4 100644
>>>> --- a/arch/x86/include/asm/tlbflush.h
>>>> +++ b/arch/x86/include/asm/tlbflush.h
>>>> @@ -264,7 +264,8 @@ static inline u64 inc_mm_tlb_gen(struct mm_struct *mm)
>>>> }
>>>>
>>>> static inline void arch_tlbbatch_add_mm(struct arch_tlbflush_unmap_batch *batch,
>>>> -                                    struct mm_struct *mm)
>>>> +                                    struct mm_struct *mm,
>>>> +                                    unsigned long uaddr)
>>>
>>> Logic-wise it looks fine. I notice the “v6", and it should not be blocking,
>>> but I would note that the name "arch_tlbbatch_add_mm()” does not make much
>>> sense once the function also takes an address.
>>
>> ok the add_mm should still apply to x86 since the address is not used, but not for arm64.
>>
>>> It could’ve been something like arch_set_tlb_ubc_flush_pending() but that’s
>>> too long. I’m not very good with naming, but the current name is not great.
>>
>> What about arch_tlbbatch_add_pending()? Considering the x86 is pending the flush operation
>> while arm64 is pending the sychronization operation, arch_tlbbatch_add_pending() should
>> make sense to both.
> 
> Sounds reasonable. Thanks.

+1, agreed.