linux-kernel - Re: [PATCH 1/2] arm64: dts: qcom: sm8550: Add USB PHYs and controller nodes

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Date:   Wed, 16 Nov 2022 14:42:09 +0100
From:   Johan Hovold <johan@...nel.org>
To:     Abel Vesa <abel.vesa@...aro.org>
Cc:     Andy Gross <agross@...nel.org>,
        Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konrad.dybcio@...aro.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        devicetree@...r.kernel.org, linux-arm-msm@...r.kernel.org
Subject: Re: [PATCH 1/2] arm64: dts: qcom: sm8550: Add USB PHYs and
 controller nodes

On Wed, Nov 16, 2022 at 03:22:11PM +0200, Abel Vesa wrote:
> Add USB host controller and PHY nodes.
> 
> Signed-off-by: Abel Vesa <abel.vesa@...aro.org>
> ---
>  arch/arm64/boot/dts/qcom/sm8550.dtsi | 99 ++++++++++++++++++++++++++++
>  1 file changed, 99 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index 07ba709ca35f..1b62395fe101 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -1460,6 +1460,105 @@ opp-202000000 {
>  			};
>  		};
>  
> +		usb_1_hsphy: phy@...3000 {
> +			compatible = "qcom,sm8550-snps-eusb2-phy";
> +			reg = <0x0 0x088e3000 0x0 0x154>;
> +			status = "disabled";
> +			#phy-cells = <0>;
> +
> +			clocks = <&tcsr TCSR_USB2_CLKREF_EN>;
> +			clock-names = "ref";
> +
> +			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
> +		};
> +
> +		usb_1_qmpphy: phy-wrapper@...9000 {
> +			compatible = "qcom,sm8550-qmp-usb3-phy";

Where's the corresponding binding update?

> +			reg = <0x0 0x088e9000 0x0 0x200>,
> +			      <0x0 0x088e8000 0x0 0x20>;
> +			status = "disabled";
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			ranges;
> +
> +			clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
> +				 <&rpmhcc RPMH_CXO_PAD_CLK>,
> +				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
> +			clock-names = "aux", "ref_clk_src", "com_aux";

Don't you have a dedicated ref clk? In any case, ref_clk_src should not
be here (either rename it 'ref' or replace it).

> +
> +			resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
> +				<&gcc GCC_USB3_PHY_PRIM_BCR>;
> +			reset-names = "phy", "common";
> +			power-domains = <&gcc USB3_PHY_GDSC>;
> +
> +			usb_1_ssphy: phy@...9200 {
> +				reg = <0x0 0x088e9200 0x0 0x200>,
> +				      <0x0 0x088e9400 0x0 0x200>,
> +				      <0x0 0x088e9c00 0x0 0x400>,
> +				      <0x0 0x088e9600 0x0 0x200>,
> +				      <0x0 0x088e9800 0x0 0x200>,
> +				      <0x0 0x088e9a00 0x0 0x100>;
> +				#phy-cells = <0>;
> +				#clock-cells = <0>;
> +				clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
> +				clock-names = "pipe0";
> +				clock-output-names = "usb3_phy_pipe_clk_src";
> +			};

As for UFS and PCIe these PHY nodes should be updated to use the new
binding scheme which drops the child node and individual register
descriptions (cf. sc8280xp).

> +		};

Johan