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Message-Id: <20221116103146.2556846-3-abel.vesa@linaro.org>
Date: Wed, 16 Nov 2022 12:31:38 +0200
From: Abel Vesa <abel.vesa@...aro.org>
To: Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
Neil Armstrong <neil.armstrong@...aro.org>
Cc: linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
"vkoul@...nel.org" <vkoul@...nel.org>,
Srinivas Kandagatla <srinivas.kandagatla@...aro.org>
Subject: [PATCH 02/10] arm64: dts: qcom: Add base SM8550 dtsi
Add base dtsi for SM8550 SoC and includes base description of
CPUs, GCC, RPMHCC, UART, interrupt controller, TLMM, reserved
memory, RPMh PD, TCSRCC, ITS, IPCC, AOSS QMP, LLCC, cpufreq,
interconnect, thermal sensor, cpu cooling maps and SMMU nodes
which helps boot to shell with console on boards with this SoC.
Co-developed-by: Neil Armstrong <neil.armstrong@...aro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@...aro.org>
Signed-off-by: Abel Vesa <abel.vesa@...aro.org>
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 3986 ++++++++++++++++++++++++++
1 file changed, 3986 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/sm8550.dtsi
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
new file mode 100644
index 000000000000..07ba709ca35f
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -0,0 +1,3986 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2022, Linaro Limited
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,gcc-sm8550.h>
+#include <dt-bindings/clock/qcom,tcsrcc-sm8550.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/dma/qcom-gpi.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/mailbox/qcom-ipcc.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/interconnect/qcom,sm8550.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+ interrupt-parent = <&intc>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ chosen { };
+
+ clocks {
+ xo_board: xo-board {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <76800000>;
+ };
+
+ pcie_1_phy_aux_clk: pcie-1-phy-aux-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1000>;
+ };
+
+ sleep_clk: sleep-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32000>;
+ };
+
+ ufs_phy_rx_symbol_0_clk: ufs-phy-rx-symbol-0-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1000>;
+ };
+
+ ufs_phy_rx_symbol_1_clk: ufs-phy-rx-symbol-1-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1000>;
+ };
+
+ ufs_phy_tx_symbol_0_clk: ufs-phy-tx-symbol-0-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1000>;
+ };
+
+ usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3-phy-wrapper-gcc-usb30-pipe_clk {
+ compatible = "fixed-clock";
+ clock-frequency = <1000>;
+ #clock-cells = <0>;
+ };
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "qcom,kryo";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ power-domains = <&CPU_PD0>;
+ power-domain-names = "psci";
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ #cooling-cells = <2>;
+ L2_0: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ L3_0: l3-cache {
+ compatible = "cache";
+ };
+ };
+ };
+
+ CPU1: cpu@100 {
+ device_type = "cpu";
+ compatible = "qcom,kryo";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ next-level-cache = <&L2_100>;
+ power-domains = <&CPU_PD1>;
+ power-domain-names = "psci";
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ #cooling-cells = <2>;
+ L2_100: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU2: cpu@200 {
+ device_type = "cpu";
+ compatible = "qcom,kryo";
+ reg = <0x0 0x200>;
+ enable-method = "psci";
+ next-level-cache = <&L2_200>;
+ power-domains = <&CPU_PD2>;
+ power-domain-names = "psci";
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ #cooling-cells = <2>;
+ L2_200: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU3: cpu@300 {
+ device_type = "cpu";
+ compatible = "qcom,kryo";
+ reg = <0x0 0x300>;
+ enable-method = "psci";
+ next-level-cache = <&L2_300>;
+ power-domains = <&CPU_PD3>;
+ power-domain-names = "psci";
+ qcom,freq-domain = <&cpufreq_hw 1>;
+ capacity-dmips-mhz = <1792>;
+ dynamic-power-coefficient = <270>;
+ #cooling-cells = <2>;
+ L2_300: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU4: cpu@400 {
+ device_type = "cpu";
+ compatible = "qcom,kryo";
+ reg = <0x0 0x400>;
+ enable-method = "psci";
+ next-level-cache = <&L2_400>;
+ power-domains = <&CPU_PD4>;
+ power-domain-names = "psci";
+ qcom,freq-domain = <&cpufreq_hw 1>;
+ capacity-dmips-mhz = <1792>;
+ dynamic-power-coefficient = <270>;
+ #cooling-cells = <2>;
+ L2_400: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU5: cpu@500 {
+ device_type = "cpu";
+ compatible = "qcom,kryo";
+ reg = <0x0 0x500>;
+ enable-method = "psci";
+ next-level-cache = <&L2_500>;
+ power-domains = <&CPU_PD5>;
+ power-domain-names = "psci";
+ qcom,freq-domain = <&cpufreq_hw 1>;
+ capacity-dmips-mhz = <1792>;
+ dynamic-power-coefficient = <270>;
+ #cooling-cells = <2>;
+ L2_500: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU6: cpu@600 {
+ device_type = "cpu";
+ compatible = "qcom,kryo";
+ reg = <0x0 0x600>;
+ enable-method = "psci";
+ next-level-cache = <&L2_600>;
+ power-domains = <&CPU_PD6>;
+ power-domain-names = "psci";
+ qcom,freq-domain = <&cpufreq_hw 1>;
+ capacity-dmips-mhz = <1792>;
+ dynamic-power-coefficient = <270>;
+ #cooling-cells = <2>;
+ L2_600: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU7: cpu@700 {
+ device_type = "cpu";
+ compatible = "qcom,kryo";
+ reg = <0x0 0x700>;
+ enable-method = "psci";
+ next-level-cache = <&L2_700>;
+ power-domains = <&CPU_PD7>;
+ power-domain-names = "psci";
+ qcom,freq-domain = <&cpufreq_hw 2>;
+ capacity-dmips-mhz = <1894>;
+ dynamic-power-coefficient = <588>;
+ #cooling-cells = <2>;
+ L2_700: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+
+ core1 {
+ cpu = <&CPU1>;
+ };
+
+ core2 {
+ cpu = <&CPU2>;
+ };
+
+ core3 {
+ cpu = <&CPU3>;
+ };
+
+ core4 {
+ cpu = <&CPU4>;
+ };
+
+ core5 {
+ cpu = <&CPU5>;
+ };
+
+ core6 {
+ cpu = <&CPU6>;
+ };
+
+ core7 {
+ cpu = <&CPU7>;
+ };
+ };
+ };
+
+ idle-states {
+ entry-method = "psci";
+
+ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
+ compatible = "arm,idle-state";
+ idle-state-name = "silver-rail-power-collapse";
+ arm,psci-suspend-param = <0x40000004>;
+ entry-latency-us = <800>;
+ exit-latency-us = <750>;
+ min-residency-us = <4090>;
+ local-timer-stop;
+ };
+
+ BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
+ compatible = "arm,idle-state";
+ idle-state-name = "gold-rail-power-collapse";
+ arm,psci-suspend-param = <0x40000004>;
+ entry-latency-us = <600>;
+ exit-latency-us = <1550>;
+ min-residency-us = <4791>;
+ local-timer-stop;
+ };
+ };
+
+ domain-idle-states {
+ CLUSTER_SLEEP_0: cluster-sleep-0 {
+ compatible = "domain-idle-state";
+ arm,psci-suspend-param = <0x41000044>;
+ entry-latency-us = <1050>;
+ exit-latency-us = <2500>;
+ min-residency-us = <5309>;
+ };
+
+ CLUSTER_SLEEP_1: cluster-sleep-1 {
+ compatible = "domain-idle-state";
+ arm,psci-suspend-param = <0x4100c344>;
+ entry-latency-us = <2700>;
+ exit-latency-us = <3500>;
+ min-residency-us = <13959>;
+ };
+ };
+ };
+
+ firmware {
+ scm: scm {
+ compatible = "qcom,scm-sm8550", "qcom,scm";
+ };
+ };
+
+ clk_virt: interconnect-0 {
+ compatible = "qcom,sm8550-clk-virt";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ mc_virt: interconnect-1 {
+ compatible = "qcom,sm8550-mc-virt";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ memory@...00000 {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the size */
+ reg = <0x0 0xa0000000 0x0 0x0>;
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+
+ CPU_PD0: power-domain-cpu0 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
+ };
+
+ CPU_PD1: power-domain-cpu1 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
+ };
+
+ CPU_PD2: power-domain-cpu2 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
+ };
+
+ CPU_PD3: power-domain-cpu3 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&BIG_CPU_SLEEP_0>;
+ };
+
+ CPU_PD4: power-domain-cpu4 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&BIG_CPU_SLEEP_0>;
+ };
+
+ CPU_PD5: power-domain-cpu5 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&BIG_CPU_SLEEP_0>;
+ };
+
+ CPU_PD6: power-domain-cpu6 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&BIG_CPU_SLEEP_0>;
+ };
+
+ CPU_PD7: power-domain-cpu7 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&BIG_CPU_SLEEP_0>;
+ };
+
+ CLUSTER_PD: power-domain-cluster {
+ #power-domain-cells = <0>;
+ domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
+ };
+ };
+
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ hyp_mem: hyp-region@...00000 {
+ reg = <0x0 0x80000000 0x0 0xa00000>;
+ no-map;
+ };
+
+ cpusys_vm_mem: cpusys-vm-region@...00000 {
+ reg = <0x0 0x80a00000 0x0 0x400000>;
+ no-map;
+ };
+
+ hyp_tags_mem: hyp-tags-region@...00000 {
+ reg = <0x0 0x80e00000 0x0 0x3d0000>;
+ no-map;
+ };
+
+ xbl_sc_mem: xbl-sc-region@...00000 {
+ reg = <0x0 0xd8100000 0x0 0x40000>;
+ no-map;
+ };
+
+
+ hyp_tags_reserved_mem: hyp-tags-reserved-region@...d0000 {
+ reg = <0x0 0x811d0000 0x0 0x30000>;
+ no-map;
+ };
+
+ /* merged xbl_dt_log, xbl_ramdump, aop_image */
+ xbl_dt_log_merged_mem: xbl-dt-log-merged-region@...00000 {
+ reg = <0x0 0x81a00000 0x0 0x260000>;
+ no-map;
+ };
+
+ aop_cmd_db_mem: aop-cmd-db-region@...60000 {
+ compatible = "qcom,cmd-db";
+ reg = <0x0 0x81c60000 0x0 0x20000>;
+ no-map;
+ };
+
+ /* merged aop_config, tme_crash_dump, tme_log, uefi_log */
+ aop_config_merged_mem: aop-config-merged-region@...80000 {
+ reg = <0x0 0x81c80000 0x0 0x74000>;
+ no-map;
+ };
+
+ /* secdata region can be reused by apps */
+ smem: smem-region@...00000 {
+ compatible = "qcom,smem";
+ reg = <0x0 0x81d00000 0x0 0x200000>;
+ hwlocks = <&tcsr_mutex 3>;
+ no-map;
+ };
+
+ adsp_mhi_mem: adsp-mhi-region@...00000 {
+ reg = <0x0 0x81f00000 0x0 0x20000>;
+ no-map;
+ };
+
+ global_sync_mem: global-sync-region@...00000 {
+ reg = <0x0 0x82600000 0x0 0x100000>;
+ no-map;
+ };
+
+ tz_stat_mem: tz-stat-region@...00000 {
+ reg = <0x0 0x82700000 0x0 0x100000>;
+ no-map;
+ };
+
+ cdsp_secure_heap_mem: cdsp-secure-heap-region@...00000 {
+ reg = <0x0 0x82800000 0x0 0x4600000>;
+ no-map;
+ };
+
+ mpss_mem: mpss-region@...00000 {
+ reg = <0x0 0x8a800000 0x0 0x10800000>;
+ no-map;
+ };
+
+ q6_mpss_dtb_mem: q6-mpss-dtb-region@...00000 {
+ reg = <0x0 0x9b000000 0x0 0x80000>;
+ no-map;
+ };
+
+ ipa_fw_mem: ipa-fw-region@...80000 {
+ reg = <0x0 0x9b080000 0x0 0x10000>;
+ no-map;
+ };
+
+ ipa_gsi_mem: ipa-gsi-region@...90000 {
+ reg = <0x0 0x9b090000 0x0 0xa000>;
+ no-map;
+ };
+
+ gpu_micro_code_mem: gpu-micro-code-region@...9a000 {
+ reg = <0x0 0x9b09a000 0x0 0x2000>;
+ no-map;
+ };
+
+ spss_region_mem: spss-region@...00000 {
+ reg = <0x0 0x9b100000 0x0 0x180000>;
+ no-map;
+ };
+
+ /* First part of the "SPU secure shared memory" region */
+ spu_tz_shared_mem: spu-tz-shared-region@...80000 {
+ reg = <0x0 0x9b280000 0x0 0x60000>;
+ no-map;
+ };
+
+ /* Second part of the "SPU secure shared memory" region */
+ spu_modem_shared_mem: spu-modem-shared-region@...e0000 {
+ reg = <0x0 0x9b2e0000 0x0 0x20000>;
+ no-map;
+ };
+
+ camera_mem: camera-region@...00000 {
+ reg = <0x0 0x9b300000 0x0 0x800000>;
+ no-map;
+ };
+
+ video_mem: video-region@...00000 {
+ reg = <0x0 0x9bb00000 0x0 0x700000>;
+ no-map;
+ };
+
+ cvp_mem: cvp-region@...00000 {
+ reg = <0x0 0x9c200000 0x0 0x700000>;
+ no-map;
+ };
+
+ cdsp_mem: cdsp-region@...00000 {
+ reg = <0x0 0x9c900000 0x0 0x2000000>;
+ no-map;
+ };
+
+ q6_cdsp_dtb_mem: q6-cdsp-dtb-region@...00000 {
+ reg = <0x0 0x9e900000 0x0 0x80000>;
+ no-map;
+ };
+
+ q6_adsp_dtb_mem: q6-adsp-dtb-region@...80000 {
+ reg = <0x0 0x9e980000 0x0 0x80000>;
+ no-map;
+ };
+
+ adspslpi_mem: adspslpi-region@...00000 {
+ reg = <0x0 0x9ea00000 0x0 0x4080000>;
+ no-map;
+ };
+
+ /* uefi region can be reused by apps */
+
+ /* Linux kernel image is loaded at 0xa8000000 */
+
+ mpss_dsm_mem: mpss-dsm-region@...00000 {
+ compatible = "qcom,mpss-dsm-mem";
+ reg = <0x0 0xd4d00000 0x0 0x3300000>;
+ no-map;
+ };
+
+ tz_reserved_mem: tz-reserved-region@...00000 {
+ reg = <0x0 0xd8000000 0x0 0x100000>;
+ no-map;
+ };
+
+ cpucp_fw_mem: cpucp-fw-region@...40000 {
+ reg = <0x0 0xd8140000 0x0 0x1c0000>;
+ no-map;
+ };
+
+ qtee_mem: qtee-region@...00000 {
+ reg = <0x0 0xd8300000 0x0 0x500000>;
+ no-map;
+ };
+
+ ta_mem: ta-region@...00000 {
+ reg = <0x0 0xd8800000 0x0 0x8a00000>;
+ no-map;
+ };
+
+ tz_tags_mem: tz-tags-region@...00000 {
+ reg = <0x0 0xe1200000 0x0 0x2740000>;
+ no-map;
+ };
+
+ hwfence_shbuf: hwfence-shbuf-region@...40000 {
+ reg = <0x0 0xe6440000 0x0 0x279000>;
+ no-map;
+ };
+
+ trust_ui_vm_mem: trust-ui-vm-region@...00000 {
+ reg = <0x0 0xf3600000 0x0 0x4aee000>;
+ no-map;
+ };
+
+ trust_ui_vm_dump: trust-ui-vm-dump-region@...ee000 {
+ reg = <0x0 0xf80ee000 0x0 0x1000>;
+ no-map;
+ };
+
+ trust_ui_vm_qrtr: trust-ui-vm-qrt-region@...ef000 {
+ reg = <0x0 0xf80ef000 0x0 0x9000>;
+ no-map;
+ };
+
+ trust_ui_vm_vblk0_ring: trust-ui-vm-vblk0-ring-region@...f8000 {
+ reg = <0x0 0xf80f8000 0x0 0x4000>;
+ no-map;
+ };
+
+ trust_ui_vm_vblk1_ring: trust-ui-vm-vblk1-ring-region@...fc000 {
+ reg = <0x0 0xf80fc000 0x0 0x4000>;
+ no-map;
+ };
+
+ trust_ui_vm_swiotlb: trust-ui-vm-swiotlb-region@...00000 {
+ reg = <0x0 0xf8100000 0x0 0x100000>;
+ no-map;
+ };
+
+ oem_vm_mem: oem-vm-region@...00000 {
+ reg = <0x0 0xf8400000 0x0 0x4800000>;
+ no-map;
+ };
+
+ oem_vm_vblk0_ring: oem-vm-vblk0-ring-region@...00000 {
+ reg = <0x0 0xfcc00000 0x0 0x4000>;
+ no-map;
+ };
+
+ oem_vm_swiotlb: oem-vm-swiotlb-region@...04000 {
+ reg = <0x0 0xfcc04000 0x0 0x100000>;
+ no-map;
+ };
+
+ hyp_ext_tags_mem: hyp-ext-tags-region@...00000 {
+ reg = <0x0 0xfce00000 0x0 0x2900000>;
+ no-map;
+ };
+
+ hyp_ext_reserved_mem: hyp-ext-reserved-region@...00000 {
+ reg = <0x0 0xff700000 0x0 0x100000>;
+ no-map;
+ };
+ };
+
+ soc: soc@0 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0 0 0 0 0x10 0>;
+ dma-ranges = <0 0 0 0 0x10 0>;
+ compatible = "simple-bus";
+
+ gcc: clock-controller@...000 {
+ compatible = "qcom,sm8550-gcc";
+ reg = <0x0 0x00100000 0x0 0x1f4200>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ clock-names = "bi_tcxo", "sleep_clk",
+ "pcie_1_phy_aux_clk",
+ "ufs_phy_rx_symbol_0_clk",
+ "ufs_phy_rx_symbol_1_clk",
+ "ufs_phy_tx_symbol_0_clk",
+ "usb3_phy_wrapper_gcc_usb30_pipe_clk";
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>,
+ <&pcie_1_phy_aux_clk>,
+ <&ufs_phy_rx_symbol_0_clk>,
+ <&ufs_phy_rx_symbol_1_clk>,
+ <&ufs_phy_tx_symbol_0_clk>,
+ <&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
+ };
+
+ ipcc: mailbox@...000 {
+ compatible = "qcom,sm8550-ipcc", "qcom,ipcc";
+ reg = <0x0 0x00408000 0x0 0x1000>;
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #mbox-cells = <2>;
+ };
+
+ gpi_dma2: dma-controller@...000 {
+ compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma";
+ #dma-cells = <3>;
+ reg = <0x0 0x00800000 0x0 0x60000>;
+ interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <12>;
+ dma-channel-mask = <0x3e>;
+ iommus = <&apps_smmu 0x436 0x0>;
+ status = "disabled";
+ };
+
+ qupv3_id_1: geniqup@...000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x0 0x008c0000 0x0 0x2000>;
+ clock-names = "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+ iommus = <&apps_smmu 0x423 0x0>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ i2c8: i2c@...000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00880000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c8_data_clk>;
+ interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
+ <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 0 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi8: spi@...000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x00880000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
+ interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
+ <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 0 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c9: i2c@...000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00884000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c9_data_clk>;
+ interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
+ <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 1 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi9: spi@...000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x00884000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
+ interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
+ <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 1 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c10: i2c@...000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00888000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c10_data_clk>;
+ interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
+ <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 2 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi10: spi@...000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x00888000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
+ interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
+ <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 2 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c11: i2c@...000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x0088c000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c11_data_clk>;
+ interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
+ <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 3 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi11: spi@...000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x0088c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+ interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
+ <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 3 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c12: i2c@...000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00890000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c12_data_clk>;
+ interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
+ <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 4 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi12: spi@...000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00890000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
+ interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
+ <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 4 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c13: i2c@...000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00894000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c13_data_clk>;
+ interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
+ <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 5 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi13: spi@...000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00894000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
+ interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
+ <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 5 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c15: i2c@...000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x0089c000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c15_data_clk>;
+ interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
+ <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 7 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi15: spi@...000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x0089c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
+ interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
+ <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 7 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ gpi_dma1: dma-controller@...000 {
+ compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma";
+ #dma-cells = <3>;
+ reg = <0x0 0x00a00000 0x0 0x60000>;
+ interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <12>;
+ dma-channel-mask = <0x1e>;
+ iommus = <&apps_smmu 0xb6 0x0>;
+ status = "disabled";
+ };
+
+ qupv3_id_0: geniqup@...000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x0 0x00ac0000 0x0 0x2000>;
+ clock-names = "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ iommus = <&apps_smmu 0xa3 0x0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>;
+ interconnect-names = "qup-core";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ i2c0: i2c@...000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00a80000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c0_data_clk>;
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 0 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi0: spi@...000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x00a80000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 0 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@...000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00a84000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c1_data_clk>;
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 1 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi1: spi@...000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x00a84000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 1 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@...000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00a88000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c2_data_clk>;
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 2 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi2: spi@...000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x00a88000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 2 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@...000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00a8c000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c3_data_clk>;
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 3 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi3: spi@...000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x00a8c000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 3 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@...000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00a90000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c4_data_clk>;
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 4 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi4: spi@...000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x00a90000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 4 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@...000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a94000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c5_data_clk>;
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 5 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi5: spi@...000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x00a94000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 5 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c6: i2c@...000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a98000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c6_data_clk>;
+ interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 6 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi6: spi@...000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x00a98000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+ interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 6 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ uart7: serial@...000 {
+ compatible = "qcom,geni-debug-uart";
+ reg = <0x0 0x00a9c000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart7_default>;
+ interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
+ interconnect-names = "qup-core", "qup-config";
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ cnoc_main: interconnect@...0000 {
+ compatible = "qcom,sm8550-cnoc-main";
+ reg = <0x0 0x01500000 0x0 0x13080>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ config_noc: interconnect@...0000 {
+ compatible = "qcom,sm8550-config-noc";
+ reg = <0x0 0x01600000 0x0 0x6200>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ system_noc: interconnect@...0000 {
+ compatible = "qcom,sm8550-system-noc";
+ reg = <0x0 0x01680000 0x0 0x1D080>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ pcie_noc: interconnect@...0000 {
+ compatible = "qcom,sm8550-pcie-anoc";
+ reg = <0x0 0x016c0000 0x0 0x12200>;
+ #interconnect-cells = <2>;
+ clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
+ <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ aggre1_noc: interconnect@...0000 {
+ compatible = "qcom,sm8550-aggre1-noc";
+ reg = <0x0 0x016e0000 0x0 0x14400>;
+ #interconnect-cells = <2>;
+ clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ aggre2_noc: interconnect@...0000 {
+ compatible = "qcom,sm8550-aggre2-noc";
+ reg = <0x0 0x01700000 0x0 0x1E400>;
+ #interconnect-cells = <2>;
+ clocks = <&rpmhcc RPMH_IPA_CLK>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ mmss_noc: interconnect@...0000 {
+ compatible = "qcom,sm8550-mmss-noc";
+ reg = <0x0 0x01780000 0x0 0x5B800>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ tcsr_mutex: hwlock@...0000 {
+ compatible = "qcom,tcsr-mutex";
+ reg = <0x0 0x01f40000 0x0 0x20000>;
+ #hwlock-cells = <1>;
+ };
+
+ tcsr: clock-controller@...0000 {
+ compatible = "qcom,sm8550-tcsrcc", "syscon";
+ reg = <0x0 0x01fc0000 0x0 0x30000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_PAD_CLK>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ lpass_lpiaon_noc: interconnect@...0000 {
+ compatible = "qcom,sm8550-lpass-lpiaon-noc";
+ reg = <0x0 0x07400000 0x0 0x19080>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ lpass_lpicx_noc: interconnect@...0000 {
+ compatible = "qcom,sm8550-lpass-lpicx-noc";
+ reg = <0x0 0x07430000 0x0 0x3A200>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ lpass_ag_noc: interconnect@...0000 {
+ compatible = "qcom,sm8550-lpass-ag-noc";
+ reg = <0x0 0x07e40000 0x0 0xE080>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ sdhc_2: mmc@...4000 {
+ compatible = "qcom,sm8550-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0x0 0x08804000 0x0 0x1000>;
+
+ interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+ <&gcc GCC_SDCC2_APPS_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "core", "xo";
+ iommus = <&apps_smmu 0x540 0x0>;
+ qcom,dll-config = <0x0007642c>;
+ qcom,ddr-config = <0x80040868>;
+ power-domains = <&rpmhpd SM8550_CX>;
+ operating-points-v2 = <&sdhc2_opp_table>;
+
+ interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
+ interconnect-names = "sdhc-ddr", "cpu-sdhc";
+
+ /* Forbid SDR104/SDR50 - broken hw! */
+ sdhci-caps-mask = <0x3 0x0>;
+
+ status = "disabled";
+
+ sdhc2_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-19200000 {
+ opp-hz = /bits/ 64 <19200000>;
+ required-opps = <&rpmhpd_opp_min_svs>;
+ };
+
+ opp-50000000 {
+ opp-hz = /bits/ 64 <50000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-202000000 {
+ opp-hz = /bits/ 64 <202000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+ };
+ };
+
+ pdc: interrupt-controller@...0000 {
+ compatible = "qcom,sm8550-pdc", "qcom,pdc";
+ reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
+ qcom,pdc-ranges = <0 480 94>, <94 609 31>,
+ <125 63 1>, <126 716 12>,
+ <138 251 5>;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&intc>;
+ interrupt-controller;
+ };
+
+ tsens0: thermal-sensor@...1000 {
+ compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
+ reg = <0 0x0c271000 0 0x1000>, /* TM */
+ <0 0x0c222000 0 0x1000>; /* SROT */
+ #qcom,sensors = <16>;
+ interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow", "critical";
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens1: thermal-sensor@...2000 {
+ compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
+ reg = <0 0x0c272000 0 0x1000>, /* TM */
+ <0 0x0c223000 0 0x1000>; /* SROT */
+ #qcom,sensors = <16>;
+ interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow", "critical";
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens2: thermal-sensor@...3000 {
+ compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
+ reg = <0 0x0c273000 0 0x1000>, /* TM */
+ <0 0x0c224000 0 0x1000>; /* SROT */
+ #qcom,sensors = <16>;
+ interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow", "critical";
+ #thermal-sensor-cells = <1>;
+ };
+
+ aoss_qmp: power-controller@...0000 {
+ compatible = "qcom,sm8550-aoss-qmp", "qcom,aoss-qmp";
+ reg = <0 0x0c300000 0 0x400>;
+ interrupt-parent = <&ipcc>;
+ interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ #clock-cells = <0>;
+ };
+
+ sram@...0000 {
+ compatible = "qcom,rpmh-stats";
+ reg = <0x0 0x0c3f0000 0x0 0x400>;
+ };
+
+ spmi_bus: spmi@...0000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0x0 0x0c400000 0x0 0x3000>,
+ <0x0 0x0c500000 0x0 0x4000000>,
+ <0x0 0x0c440000 0x0 0x80000>,
+ <0x0 0x0c4c0000 0x0 0x20000>,
+ <0x0 0x0c42d000 0x0 0x4000>;
+ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+ interrupt-names = "periph_irq";
+ interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ qcom,bus-id = <0>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ };
+
+ tlmm: pinctrl@...0000 {
+ compatible = "qcom,sm8550-tlmm";
+ reg = <0x0 0x0f100000 0x0 0x300000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 211>;
+ wakeup-parent = <&pdc>;
+
+ hub_i2c0_data_clk: hub-i2c0-data-clk-state {
+ scl-pins {
+ pins = "gpio17";
+ function = "i2chub0_se0";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ sda-pins {
+ pins = "gpio16";
+ function = "i2chub0_se0";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ hub_i2c1_data_clk: hub-i2c1-data-clk-state {
+ scl-pins {
+ pins = "gpio19";
+ function = "i2chub0_se1";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ sda-pins {
+ pins = "gpio18";
+ function = "i2chub0_se1";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ hub_i2c2_data_clk: hub-i2c2-data-clk-state {
+ scl-pins {
+ pins = "gpio21";
+ function = "i2chub0_se2";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ sda-pins {
+ pins = "gpio20";
+ function = "i2chub0_se2";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ hub_i2c3_data_clk: hub-i2c3-data-clk-state {
+ scl-pins {
+ pins = "gpio23";
+ function = "i2chub0_se3";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ sda-pins {
+ pins = "gpio22";
+ function = "i2chub0_se3";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ hub_i2c4_data_clk: hub-i2c4-data-clk-state {
+ scl-pins {
+ pins = "gpio5";
+ function = "i2chub0_se4";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ sda-pins {
+ pins = "gpio4";
+ function = "i2chub0_se4";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ hub_i2c5_data_clk: hub-i2c5-data-clk-state {
+ scl-pins {
+ pins = "gpio7";
+ function = "i2chub0_se5";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ sda-pins {
+ pins = "gpio6";
+ function = "i2chub0_se5";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ hub_i2c6_data_clk: hub-i2c6-data-clk-state {
+ scl-pins {
+ pins = "gpio9";
+ function = "i2chub0_se6";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ sda-pins {
+ pins = "gpio8";
+ function = "i2chub0_se6";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ hub_i2c7_data_clk: hub-i2c7-data-clk-state {
+ scl-pins {
+ pins = "gpio11";
+ function = "i2chub0_se7";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ sda-pins {
+ pins = "gpio10";
+ function = "i2chub0_se7";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ hub_i2c8_data_clk: hub-i2c8-data-clk-state {
+ scl-pins {
+ pins = "gpio207";
+ function = "i2chub0_se8";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ sda-pins {
+ pins = "gpio206";
+ function = "i2chub0_se8";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ hub_i2c9_data_clk: hub-i2c9-data-clk-state {
+ scl-pins {
+ pins = "gpio85";
+ function = "i2chub0_se9";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ sda-pins {
+ pins = "gpio84";
+ function = "i2chub0_se9";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ pcie0_default_state: pcie0-default-state {
+ perst-pins {
+ pins = "gpio94";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ clkreq-pins {
+ pins = "gpio95";
+ function = "pcie0_clk_req_n";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ wake-pins {
+ pins = "gpio96";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ pcie1_default_state: pcie1-default-state {
+ perst-pins {
+ pins = "gpio97";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ clkreq-pins {
+ pins = "gpio98";
+ function = "pcie1_clk_req_n";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ wake-pins {
+ pins = "gpio99";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ qup_i2c0_data_clk: qup-i2c0-data-clk-state {
+ scl-pins {
+ pins = "gpio29";
+ function = "qup1_se0";
+ drive-strength = <2>;
+ bias-pull-up;
+ qcom,i2c-pull;
+ };
+
+ sda-pins {
+ pins = "gpio28";
+ function = "qup1_se0";
+ drive-strength = <2>;
+ bias-pull-up;
+ qcom,i2c-pull;
+ };
+ };
+
+ qup_i2c1_data_clk: qup-i2c1-data-clk-state {
+ scl-pins {
+ pins = "gpio33";
+ function = "qup1_se1";
+ drive-strength = <2>;
+ bias-pull-up;
+ qcom,i2c-pull;
+ };
+
+ sda-pins {
+ pins = "gpio32";
+ function = "qup1_se1";
+ drive-strength = <2>;
+ bias-pull-up;
+ qcom,i2c-pull;
+ };
+ };
+
+ qup_i2c2_data_clk: qup-i2c2-data-clk-state {
+ scl-pins {
+ pins = "gpio37";
+ function = "qup1_se2";
+ drive-strength = <2>;
+ bias-pull-up;
+ qcom,i2c-pull;
+ };
+
+ sda-pins {
+ pins = "gpio36";
+ function = "qup1_se2";
+ drive-strength = <2>;
+ bias-pull-up;
+ qcom,i2c-pull;
+ };
+ };
+
+ qup_i2c3_data_clk: qup-i2c3-data-clk-state {
+ scl-pins {
+ pins = "gpio41";
+ function = "qup1_se3";
+ drive-strength = <2>;
+ bias-pull-up;
+ qcom,i2c-pull;
+ };
+
+ sda-pins {
+ pins = "gpio40";
+ function = "qup1_se3";
+ drive-strength = <2>;
+ bias-pull-up;
+ qcom,i2c-pull;
+ };
+ };
+
+ qup_i2c4_data_clk: qup-i2c4-data-clk-state {
+ scl-pins {
+ pins = "gpio45";
+ function = "qup1_se4";
+ drive-strength = <2>;
+ bias-pull-up;
+ qcom,i2c-pull;
+ };
+
+ sda-pins {
+ pins = "gpio44";
+ function = "qup1_se4";
+ drive-strength = <2>;
+ bias-pull-up;
+ qcom,i2c-pull;
+ };
+ };
+
+ qup_i2c5_data_clk: qup-i2c5-data-clk-state {
+ scl-pins {
+ pins = "gpio53";
+ function = "qup1_se5";
+ drive-strength = <2>;
+ bias-pull-up;
+ qcom,i2c-pull;
+ };
+
+ sda-pins {
+ pins = "gpio52";
+ function = "qup1_se5";
+ drive-strength = <2>;
+ bias-pull-up;
+ qcom,i2c-pull;
+ };
+ };
+
+ qup_i2c6_data_clk: qup-i2c6-data-clk-state {
+ scl-pins {
+ pins = "gpio49";
+ function = "qup1_se6";
+ drive-strength = <2>;
+ bias-pull-up;
+ qcom,i2c-pull;
+ };
+
+ sda-pins {
+ pins = "gpio48";
+ function = "qup1_se6";
+ drive-strength = <2>;
+ bias-pull-up;
+ qcom,i2c-pull;
+ };
+ };
+
+ qup_i2c8_data_clk: qup-i2c8-data-clk-state {
+ scl-pins {
+ pins = "gpio57";
+ function = "qup2_se0_l1_mira";
+ drive-strength = <2>;
+ bias-pull-up;
+ qcom,i2c-pull;
+ };
+
+ sda-pins {
+ pins = "gpio56";
+ function = "qup2_se0_l0_mira";
+ drive-strength = <2>;
+ bias-pull-up;
+ qcom,i2c-pull;
+ };
+ };
+
+ qup_i2c9_data_clk: qup-i2c9-data-clk-state {
+ scl-pins {
+ pins = "gpio61";
+ function = "qup2_se1";
+ drive-strength = <2>;
+ bias-pull-up;
+ qcom,i2c-pull;
+ };
+
+ sda-pins {
+ pins = "gpio60";
+ function = "qup2_se1";
+ drive-strength = <2>;
+ bias-pull-up;
+ qcom,i2c-pull;
+ };
+ };
+
+ qup_i2c10_data_clk: qup-i2c10-data-clk-state {
+ scl-pins {
+ pins = "gpio65";
+ function = "qup2_se2";
+ drive-strength = <2>;
+ bias-pull-up;
+ qcom,i2c-pull;
+ };
+
+ sda-pins {
+ pins = "gpio64";
+ function = "qup2_se2";
+ drive-strength = <2>;
+ bias-pull-up;
+ qcom,i2c-pull;
+ };
+ };
+
+ qup_i2c11_data_clk: qup-i2c11-data-clk-state {
+ scl-pins {
+ pins = "gpio69";
+ function = "qup2_se3";
+ drive-strength = <2>;
+ bias-pull-up;
+ qcom,i2c-pull;
+ };
+
+ sda-pins {
+ pins = "gpio68";
+ function = "qup2_se3";
+ drive-strength = <2>;
+ bias-pull-up;
+ qcom,i2c-pull;
+ };
+ };
+
+ qup_i2c12_data_clk: qup-i2c12-data-clk-state {
+ scl-pins {
+ pins = "gpio3";
+ function = "qup2_se4";
+ drive-strength = <2>;
+ bias-pull-up;
+ qcom,i2c-pull;
+ };
+
+ sda-pins {
+ pins = "gpio2";
+ function = "qup2_se4";
+ drive-strength = <2>;
+ bias-pull-up;
+ qcom,i2c-pull;
+ };
+ };
+
+ qup_i2c13_data_clk: qup-i2c13-data-clk-state {
+ scl-pins {
+ pins = "gpio81";
+ function = "qup2_se5";
+ drive-strength = <2>;
+ bias-pull-up;
+ qcom,i2c-pull;
+ };
+
+ sda-pins {
+ pins = "gpio80";
+ function = "qup2_se5";
+ drive-strength = <2>;
+ bias-pull-up;
+ qcom,i2c-pull;
+ };
+ };
+
+ qup_i2c15_data_clk: qup-i2c15-data-clk-state {
+ scl-pins {
+ pins = "gpio106";
+ function = "qup2_se7";
+ drive-strength = <2>;
+ bias-pull-up;
+ qcom,i2c-pull;
+ };
+
+ sda-pins {
+ pins = "gpio72";
+ function = "qup2_se7";
+ drive-strength = <2>;
+ bias-pull-up;
+ qcom,i2c-pull;
+ };
+ };
+
+ qup_spi0_cs: qup-spi0-cs-state {
+ cs-pins {
+ pins = "gpio31";
+ function = "qup1_se0";
+ };
+ };
+
+ qup_spi0_data_clk: qup-spi0-data-clk-state {
+ clk-pins {
+ pins = "gpio30";
+ function = "qup1_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ miso-pins {
+ pins = "gpio28";
+ function = "qup1_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ mosi-pins {
+ pins = "gpio29";
+ function = "qup1_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qup_spi1_cs: qup-spi1-cs-state {
+ cs-pins {
+ pins = "gpio35";
+ function = "qup1_se1";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qup_spi1_data_clk: qup-spi1-data-clk-state {
+ clk-pins {
+ pins = "gpio34";
+ function = "qup1_se1";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ miso-pins {
+ pins = "gpio32";
+ function = "qup1_se1";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ mosi-pins {
+ pins = "gpio33";
+ function = "qup1_se1";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qup_spi2_cs: qup-spi2-cs-state {
+ cs-pins {
+ pins = "gpio39";
+ function = "qup1_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qup_spi2_data_clk: qup-spi2-data-clk-state {
+ clk-pins {
+ pins = "gpio38";
+ function = "qup1_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ miso-pins {
+ pins = "gpio36";
+ function = "qup1_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ mosi-pins {
+ pins = "gpio37";
+ function = "qup1_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qup_spi3_cs: qup-spi3-cs-state {
+ cs-pins {
+ pins = "gpio43";
+ function = "qup1_se3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qup_spi3_data_clk: qup-spi3-data-clk-state {
+ clk-pins {
+ pins = "gpio42";
+ function = "qup1_se3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ miso-pins {
+ pins = "gpio40";
+ function = "qup1_se3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ mosi-pins {
+ pins = "gpio41";
+ function = "qup1_se3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qup_spi4_cs: qup-spi4-cs-state {
+ cs-pins {
+ pins = "gpio47";
+ function = "qup1_se4";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qup_spi4_data_clk: qup-spi4-data-clk-state {
+ clk-pins {
+ pins = "gpio46";
+ function = "qup1_se4";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ miso-pins {
+ pins = "gpio44";
+ function = "qup1_se4";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ mosi-pins {
+ pins = "gpio45";
+ function = "qup1_se4";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qup_spi5_cs: qup-spi5-cs-state {
+ cs-pins {
+ pins = "gpio55";
+ function = "qup1_se5";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qup_spi5_data_clk: qup-spi5-data-clk-state {
+ clk-pins {
+ pins = "gpio54";
+ function = "qup1_se5";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ miso-pins {
+ pins = "gpio52";
+ function = "qup1_se5";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ mosi-pins {
+ pins = "gpio53";
+ function = "qup1_se5";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qup_spi6_cs: qup-spi6-cs-state {
+ cs-pins {
+ pins = "gpio51";
+ function = "qup1_se6";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qup_spi6_data_clk: qup-spi6-data-clk-state {
+ clk-pins {
+ pins = "gpio50";
+ function = "qup1_se6";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ miso-pins {
+ pins = "gpio48";
+ function = "qup1_se6";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ mosi-pins {
+ pins = "gpio49";
+ function = "qup1_se6";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qup_spi8_cs: qup-spi8-cs-state {
+ cs-pins {
+ pins = "gpio59";
+ function = "qup2_se0_l3_mira";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qup_spi8_data_clk: qup-spi8-data-clk-state {
+ clk-pins {
+ pins = "gpio58";
+ function = "qup2_se0_l2_mira";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ miso-pins {
+ pins = "gpio56";
+ function = "qup2_se0_l0_mira";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ mosi-pins {
+ pins = "gpio57";
+ function = "qup2_se0_l1_mira";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qup_spi9_cs: qup-spi9-cs-state {
+ cs-pins {
+ pins = "gpio63";
+ function = "qup2_se1";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qup_spi9_data_clk: qup-spi9-data-clk-state {
+ clk-pins {
+ pins = "gpio62";
+ function = "qup2_se1";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ miso-pins {
+ pins = "gpio60";
+ function = "qup2_se1";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ mosi-pins {
+ pins = "gpio61";
+ function = "qup2_se1";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qup_spi10_cs: qup-spi10-cs-state {
+ cs-pins {
+ pins = "gpio67";
+ function = "qup2_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qup_spi10_data_clk: qup-spi10-data-clk-state {
+ clk-pins {
+ pins = "gpio66";
+ function = "qup2_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ miso-pins {
+ pins = "gpio64";
+ function = "qup2_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ mosi-pins {
+ pins = "gpio65";
+ function = "qup2_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qup_spi11_cs: qup-spi11-cs-state {
+ cs-pins {
+ pins = "gpio71";
+ function = "qup2_se3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qup_spi11_data_clk: qup-spi11-data-clk-state {
+ clk-pins {
+ pins = "gpio70";
+ function = "qup2_se3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ miso-pins {
+ pins = "gpio68";
+ function = "qup2_se3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ mosi-pins {
+ pins = "gpio69";
+ function = "qup2_se3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qup_spi12_cs: qup-spi12-cs-state {
+ cs-pins {
+ pins = "gpio119";
+ function = "qup2_se4";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qup_spi12_data_clk: qup-spi12-data-clk-state {
+ clk-pins {
+ pins = "gpio118";
+ function = "qup2_se4";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ miso-pins {
+ pins = "gpio2";
+ function = "qup2_se4";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ mosi-pins {
+ pins = "gpio3";
+ function = "qup2_se4";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qup_spi13_cs: qup-spi13-cs-state {
+ cs-pins {
+ pins = "gpio83";
+ function = "qup2_se5";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qup_spi13_data_clk: qup-spi13-data-clk-state {
+ clk-pins {
+ pins = "gpio82";
+ function = "qup2_se5";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ miso-pins {
+ pins = "gpio80";
+ function = "qup2_se5";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ mosi-pins {
+ pins = "gpio81";
+ function = "qup2_se5";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qup_spi15_cs: qup-spi15-cs-state {
+ cs-pins {
+ pins = "gpio75";
+ function = "qup2_se7";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qup_spi15_data_clk: qup-spi15-data-clk-state {
+ clk-pins {
+ pins = "gpio74";
+ function = "qup2_se7";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ miso-pins {
+ pins = "gpio72";
+ function = "qup2_se7";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ mosi-pins {
+ pins = "gpio106";
+ function = "qup2_se7";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qup_uart7_default: qup-uart7-default-state {
+ rx-pins {
+ pins = "gpio27";
+ function = "qup1_se7";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ tx-pins {
+ pins = "gpio26";
+ function = "qup1_se7";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ sdc2_sleep: sdc2-sleep-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ cmd-pins {
+ pins = "sdc2_cmd";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ data-pins {
+ pins = "sdc2_data";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+ };
+ };
+
+ apps_smmu: iommu@...00000 {
+ compatible = "qcom,sm8550-smmu-500", "arm,mmu-500";
+ reg = <0x0 0x15000000 0x0 0x100000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ intc: interrupt-controller@...00000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ #redistributor-regions = <1>;
+ redistributor-stride = <0x0 0x40000>;
+ reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */
+ <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gic_its: msi-controller@...40000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x0 0x17140000 0x0 0x20000>;
+ msi-controller;
+ #msi-cells = <1>;
+ };
+ };
+
+ timer@...20000 {
+ compatible = "arm,armv7-timer-mem";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0 0x17420000 0x0 0x1000>;
+ ranges = <0 0 0 0x20000000>;
+
+ frame@...21000 {
+ frame-number = <0>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17421000 0x1000>,
+ <0x17422000 0x1000>;
+ };
+
+ frame@...23000 {
+ frame-number = <1>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17423000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@...25000 {
+ frame-number = <2>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17425000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@...27000 {
+ frame-number = <3>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17427000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@...29000 {
+ frame-number = <4>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17429000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@...2b000 {
+ frame-number = <5>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x1742b000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@...2d000 {
+ frame-number = <6>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x1742d000 0x1000>;
+ status = "disabled";
+ };
+ };
+
+ apps_rsc: rsc@...00000 {
+ label = "apps_rsc";
+ compatible = "qcom,rpmh-rsc";
+ reg = <0x0 0x17a00000 0x0 0x10000>,
+ <0x0 0x17a10000 0x0 0x10000>,
+ <0x0 0x17a20000 0x0 0x10000>,
+ <0x0 0x17a30000 0x0 0x10000>;
+ reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,tcs-offset = <0xd00>;
+ qcom,drv-id = <2>;
+ qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
+ <WAKE_TCS 2>, <CONTROL_TCS 0>;
+
+ apps_bcm_voter: bcm-voter {
+ compatible = "qcom,bcm-voter";
+ };
+
+ rpmhcc: clock-controller {
+ compatible = "qcom,sm8550-rpmh-clk";
+ #clock-cells = <1>;
+ clock-names = "xo";
+ clocks = <&xo_board>;
+ };
+
+ rpmhpd: power-controller {
+ compatible = "qcom,sm8550-rpmhpd";
+ #power-domain-cells = <1>;
+ operating-points-v2 = <&rpmhpd_opp_table>;
+
+ rpmhpd_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ rpmhpd_opp_ret: opp1 {
+ opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ };
+
+ rpmhpd_opp_min_svs: opp2 {
+ opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+ };
+
+ rpmhpd_opp_low_svs: opp3 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
+
+ rpmhpd_opp_svs: opp4 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+
+ rpmhpd_opp_svs_l1: opp5 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ };
+
+ rpmhpd_opp_nom: opp6 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ };
+
+ rpmhpd_opp_nom_l1: opp7 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ };
+
+ rpmhpd_opp_nom_l2: opp8 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
+ };
+
+ rpmhpd_opp_turbo: opp9 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+ };
+
+ rpmhpd_opp_turbo_l1: opp10 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ };
+ };
+ };
+ };
+
+ cpufreq_hw: cpufreq@...91000 {
+ compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss";
+ reg = <0x0 0x17D91000 0x0 0x1000>,
+ <0x0 0x17D92000 0x0 0x1000>,
+ <0x0 0x17D93000 0x0 0x1000>;
+ reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
+ clock-names = "xo", "alternate";
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
+ #freq-domain-cells = <1>;
+ };
+
+ pmu@...b6400 {
+ compatible = "qcom,sm8550-cpu-bwmon", "qcom,msm8998-bwmon";
+ reg = <0x0 0x240b6400 0x0 0x600>;
+ interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>;
+
+ operating-points-v2 = <&cpu_bwmon_opp_table>;
+
+ cpu_bwmon_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-0 {
+ opp-peak-kBps = <4577000>;
+ };
+ opp-1 {
+ opp-peak-kBps = <7110000>;
+ };
+ opp-2 {
+ opp-peak-kBps = <9155000>;
+ };
+ opp-3 {
+ opp-peak-kBps = <12298000>;
+ };
+ opp-4 {
+ opp-peak-kBps = <14236000>;
+ };
+ opp-5 {
+ opp-peak-kBps = <16265000>;
+ };
+ };
+ };
+
+ pmu@...91000 {
+ compatible = "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
+ reg = <0x0 0x24091000 0x0 0x1000>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>;
+
+ operating-points-v2 = <&llcc_bwmon_opp_table>;
+
+ llcc_bwmon_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-0 {
+ opp-peak-kBps = <2086000>;
+
+ };
+ opp-1 {
+ opp-peak-kBps = <2929000>;
+
+ };
+ opp-2 {
+ opp-peak-kBps = <5931000>;
+
+ };
+ opp-3 {
+ opp-peak-kBps = <6515000>;
+
+ };
+ opp-4 {
+ opp-peak-kBps = <7980000>;
+
+ };
+ opp-5 {
+ opp-peak-kBps = <10437000>;
+
+ };
+ opp-6 {
+ opp-peak-kBps = <12157000>;
+
+ };
+ opp-7 {
+ opp-peak-kBps = <14060000>;
+
+ };
+ opp-8 {
+ opp-peak-kBps = <16113000>;
+
+ };
+ };
+ };
+
+ gem_noc: interconnect@...00000 {
+ compatible = "qcom,sm8550-gem-noc";
+ reg = <0x0 0x24100000 0x0 0xBB800>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ system-cache-controller@...00000 {
+ compatible = "qcom,sm8550-llcc";
+ reg = <0x0 0x25000000 0x0 0x800000>,
+ <0x0 0x25800000 0x0 0x200000>;
+ reg-names = "llcc_base", "llcc_broadcast_base";
+ interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ nsp_noc: interconnect@...c0000 {
+ compatible = "qcom,sm8550-nsp-noc";
+ reg = <0x0 0x320C0000 0x0 0xE080>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+ };
+
+ thermal-zones {
+ aoss0-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 0>;
+
+ trips {
+ thermal-engine-config {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpuss0-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 1>;
+
+ trips {
+ thermal-engine-config {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpuss1-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 2>;
+
+ trips {
+ thermal-engine-config {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpuss2-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 3>;
+
+ trips {
+ thermal-engine-config {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpuss3-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 4>;
+
+ trips {
+ thermal-engine-config {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu3-top-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 5>;
+
+ trips {
+ cpu3_top_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu3_top_alert1: trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu3_top_crit: cpu-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu3-bottom-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 6>;
+
+ trips {
+ cpu3_bottom_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu3_bottom_alert1: trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu3_bottom_crit: cpu-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu4-top-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 7>;
+
+ trips {
+ cpu4_top_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu4_top_alert1: trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu4_top_crit: cpu-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu4-bottom-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 8>;
+
+ trips {
+ cpu4_bottom_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu4_bottom_alert1: trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu4_bottom_crit: cpu-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu5-top-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 9>;
+
+ trips {
+ cpu5_top_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu5_top_alert1: trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu5_top_crit: cpu-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu5-bottom-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 10>;
+
+ trips {
+ cpu5_bottom_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu5_bottom_alert1: trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu5_bottom_crit: cpu-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu6-top-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 11>;
+
+ trips {
+ cpu6_top_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu6_top_alert1: trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu6_top_crit: cpu-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu6-bottom-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 12>;
+
+ trips {
+ cpu6_bottom_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu6_bottom_alert1: trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu6_bottom_crit: cpu-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu7-top-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 13>;
+
+ trips {
+ cpu7_top_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu7_top_alert1: trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu7_top_crit: cpu-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu7-middle-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 14>;
+
+ trips {
+ cpu7_middle_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu7_middle_alert1: trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu7_middle_crit: cpu-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu7-bottom-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 15>;
+
+ trips {
+ cpu7_bottom_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu7_bottom_alert1: trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu7_bottom_crit: cpu-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ aoss1-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 0>;
+
+ trips {
+ thermal-engine-config {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu0-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 1>;
+
+ trips {
+ cpu0_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu0_alert1: trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu0_crit: cpu-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu1-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 2>;
+
+ trips {
+ cpu1_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu1_alert1: trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu1_crit: cpu-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu2-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 3>;
+
+ trips {
+ cpu2_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu2_alert1: trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu2_crit: cpu-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cdsp0-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens2 4>;
+
+ trips {
+ thermal-engine-config {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ thermal-hal-config {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cdsp0_junction_config: junction-config {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cdsp1-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens2 5>;
+
+ trips {
+ thermal-engine-config {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ thermal-hal-config {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cdsp1_junction_config: junction-config {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cdsp2-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens2 6>;
+
+ trips {
+ thermal-engine-config {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ thermal-hal-config {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cdsp2_junction_config: junction-config {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cdsp3-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens2 7>;
+
+ trips {
+ thermal-engine-config {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ thermal-hal-config {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cdsp3_junction_config: junction-config {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ video-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 8>;
+
+ trips {
+ thermal-engine-config {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ mem-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 9>;
+
+ trips {
+ thermal-engine-config {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ ddr_config0: ddr0-config {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ modem0-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 10>;
+
+ trips {
+ thermal-engine-config {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ mdmss0_config0: mdmss0-config0 {
+ temperature = <102000>;
+ hysteresis = <3000>;
+ type = "passive";
+ };
+
+ mdmss0_config1: mdmss0-config1 {
+ temperature = <105000>;
+ hysteresis = <3000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ modem1-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 11>;
+
+ trips {
+ thermal-engine-config {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ mdmss1_config0: mdmss1-config0 {
+ temperature = <102000>;
+ hysteresis = <3000>;
+ type = "passive";
+ };
+
+ mdmss1_config1: mdmss1-config1 {
+ temperature = <105000>;
+ hysteresis = <3000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ modem2-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 12>;
+
+ trips {
+ thermal-engine-config {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ mdmss2_config0: mdmss2-config0 {
+ temperature = <102000>;
+ hysteresis = <3000>;
+ type = "passive";
+ };
+
+ mdmss2_config1: mdmss2-config1 {
+ temperature = <105000>;
+ hysteresis = <3000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ modem3-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 13>;
+
+ trips {
+ thermal-engine-config {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ mdmss3_config0: mdmss3-config0 {
+ temperature = <102000>;
+ hysteresis = <3000>;
+ type = "passive";
+ };
+
+ mdmss3_config1: mdmss3-config1 {
+ temperature = <105000>;
+ hysteresis = <3000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ camera0-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 14>;
+
+ trips {
+ thermal-engine-config {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ camera1-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 15>;
+
+ trips {
+ thermal-engine-config {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ aoss2-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens2 0>;
+
+ trips {
+ thermal-engine-config {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ gpuss-0-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens2 1>;
+
+ trips {
+ thermal-engine-config {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ thermal-hal-config {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ gpu0_junction_config: junction-config {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ gpuss-1-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens2 2>;
+
+ trips {
+ thermal-engine-config {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ thermal-hal-config {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ gpu1_junction_config: junction-config {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ gpuss-2-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens2 3>;
+
+ trips {
+ thermal-engine-config {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ thermal-hal-config {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ gpu2_junction_config: junction-config {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ gpuss-3-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens2 4>;
+
+ trips {
+ thermal-engine-config {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ thermal-hal-config {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ gpu3_junction_config: junction-config {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ gpuss-4-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens2 5>;
+
+ trips {
+ thermal-engine-config {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ thermal-hal-config {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ gpu4_junction_config: junction-config {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ gpuss-5-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens2 6>;
+
+ trips {
+ thermal-engine-config {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ thermal-hal-config {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ gpu5_junction_config: junction-config {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ gpuss-6-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens2 7>;
+
+ trips {
+ thermal-engine-config {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ thermal-hal-config {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ gpu6_junction_config: junction-config {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ gpuss-7-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens2 8>;
+
+ trips {
+ thermal-engine-config {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ thermal-hal-config {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ gpu7_junction_config: junction-config {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+};
--
2.34.1
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