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Date:   Wed, 16 Nov 2022 10:27:19 +0800
From:   Jiaxi Chen <jiaxi.chen@...ux.intel.com>
To:     Borislav Petkov <bp@...en8.de>,
        Sean Christopherson <seanjc@...gle.com>
Cc:     Xiaoyao Li <xiaoyao.li@...el.com>, kvm@...r.kernel.org,
        tglx@...utronix.de, mingo@...hat.com, dave.hansen@...ux.intel.com,
        x86@...nel.org, hpa@...or.com, pbonzini@...hat.com,
        ndesaulniers@...gle.com, alexandre.belloni@...tlin.com,
        peterz@...radead.org, jpoimboe@...nel.org,
        chang.seok.bae@...el.com, pawan.kumar.gupta@...ux.intel.com,
        babu.moger@....com, jmattson@...gle.com, sandipan.das@....com,
        tony.luck@...el.com, sathyanarayanan.kuppuswamy@...ux.intel.com,
        fenghua.yu@...el.com, keescook@...omium.org, nathan@...nel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3 1/7] x86: KVM: Move existing x86 CPUID leaf
 [CPUID_7_1_EAX] to kvm-only leaf



On 11/16/2022 12:16 AM, Borislav Petkov wrote:
> On Tue, Nov 15, 2022 at 03:29:45PM +0000, Sean Christopherson wrote:
>> Heh, are any of the bits you believe Intel will add publicly documented?  :-)
>>
>> LAM could be scattered, but if more bits are expected that's probably a waste of
>> time and effort.
> 
> I'm being told the bigger part of that word is going to be used for
> either kernel or KVM bits so we might as well use it the "normal" way
> instead of doing KVM-only or scattered bits after all.
> 
> Thx.
> 
Intel published ISE spec
[https://cdrdv2.intel.com/v1/dl/getContent/671368] has documented 11
instructions for this leaf CPUID.7.1.EAX by now. Given that more bits
are going to be defined, I will enable these bits in the patch series as
v1 did and will not move them to kvm-only leaves.

By the way, Boris, what about CPUID.7.1.EDX, whether bigger part of it
is expected to be used? In intel ISE, 3 bits are defined for this word.
For now, I think put them in kvm-only subleaves as this patch series did
is a better choice. What's your opinion?

-- 
Regards,
Jiaxi

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