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Message-ID: <CA+V-a8sFfT5eUQaxQWrYraWEBDMhxDcG6fWcioV_i8aJ5Fg+3g@mail.gmail.com>
Date:   Thu, 17 Nov 2022 15:21:37 +0000
From:   "Lad, Prabhakar" <prabhakar.csengg@...il.com>
To:     Geert Uytterhoeven <geert@...ux-m68k.org>
Cc:     Thomas Gleixner <tglx@...utronix.de>,
        Marc Zyngier <maz@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Geert Uytterhoeven <geert+renesas@...der.be>,
        Magnus Damm <magnus.damm@...il.com>,
        Linus Walleij <linus.walleij@...aro.org>,
        linux-gpio@...r.kernel.org, linux-renesas-soc@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        Biju Das <biju.das.jz@...renesas.com>,
        Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH RFC 4/5] arm64: dts: renesas: r9a07g043[u]: Update pinctrl
 node to handle GPIO interrupts

Hi Geert,

Thank you for the review.

On Thu, Nov 17, 2022 at 11:20 AM Geert Uytterhoeven
<geert@...ux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Mon, Nov 7, 2022 at 6:53 PM Prabhakar <prabhakar.csengg@...il.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> >
> > Add required properties in pinctrl node to handle GPIO interrupts.
> >
> > Note as IRQC is not enabled in RZ/Five the phandle for interrupt-parent
> > is added in RZ/G2UL specific dtsi so that RZ/Five pinctrl driver
> > continues without waiting for IRQC to probe.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
>
> Thanks for your patch!
>
> > --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
> > @@ -531,6 +531,8 @@ pinctrl: pinctrl@...30000 {
> >                         gpio-controller;
> >                         #gpio-cells = <2>;
> >                         gpio-ranges = <&pinctrl 0 0 152>;
> > +                       #interrupt-cells = <2>;
> > +                       interrupt-controller;
> >                         clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
> >                         power-domains = <&cpg>;
> >                         resets = <&cpg R9A07G043_GPIO_RSTN>,
> > diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
> > index 7a8ed7ae253b..65e7b029361e 100644
> > --- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
> > @@ -98,6 +98,10 @@ &irqc {
> >         resets = <&cpg R9A07G043_IA55_RESETN>;
> >  };
> >
> > +&pinctrl {
> > +       interrupt-parent = <&irqc>;
> > +};
>
> Do you plan to move it back to the common r9a07g043.dtsi later?
Yes we should be doing that.

> Perhaps it makes sense to move the full irqc node to r9a07g043[uf].dtsi?
> There is not that much common left, even the compatible value differs.
> We don't keep the few common properties of the cpu0 node in
> r9a07g043.dtsi neither.
>
Agreed, I will move it in the next version.

Cheers,
Prabhakar

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