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Message-ID: <20221117175502.GG2350331@ls.amr.corp.intel.com>
Date: Thu, 17 Nov 2022 09:55:02 -0800
From: Isaku Yamahata <isaku.yamahata@...il.com>
To: "Huang, Kai" <kai.huang@...el.com>
Cc: "kvm@...r.kernel.org" <kvm@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"Yamahata, Isaku" <isaku.yamahata@...el.com>,
"sean.j.christopherson@...el.com" <sean.j.christopherson@...el.com>,
"pbonzini@...hat.com" <pbonzini@...hat.com>,
"Shahar, Sagi" <sagis@...gle.com>,
"Aktas, Erdem" <erdemaktas@...gle.com>,
"isaku.yamahata@...il.com" <isaku.yamahata@...il.com>,
"dmatlack@...gle.com" <dmatlack@...gle.com>,
"Christopherson,, Sean" <seanjc@...gle.com>
Subject: Re: [PATCH v10 031/108] KVM: x86/mmu: Replace hardcoded value 0 for
the initial value for SPTE
On Tue, Nov 08, 2022 at 11:33:12AM +0000,
"Huang, Kai" <kai.huang@...el.com> wrote:
> On Sat, 2022-10-29 at 23:22 -0700, isaku.yamahata@...el.com wrote:
> > The plan is to unconditionally set the "suppress #VE" bit for both AMD and
> > Intel as: 1) AMD hardware doesn't use this bit; 2) for conventional VMX
> > guests, KVM never enables the "EPT-violation #VE" in VMCS control and
> > "suppress #VE" bit is ignored by hardware.
>
> Hi Isaku,
>
> "AMD hardware doesn't use this bit" is wrong:
>
> https://lore.kernel.org/lkml/cover.1659854790.git.isaku.yamahata@intel.com/T/#m5ed59404da43677e99ac51dd1360dc22b964bcbb
Oops. I'll update the commit message.
--
Isaku Yamahata <isaku.yamahata@...il.com>
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