lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
Open Source and information security mailing list archives
| ||
|
Date: Thu, 17 Nov 2022 15:19:06 +0800 From: Perry Yuan <Perry.Yuan@....com> To: <rafael.j.wysocki@...el.com>, <ray.huang@....com>, <viresh.kumar@...aro.org>, <Mario.Limonciello@....com> CC: <Nathan.Fontenot@....com>, <Alexander.Deucher@....com>, <Deepak.Sharma@....com>, <Shimmer.Huang@....com>, <Li.Meng@....com>, <Xiaojian.Du@....com>, <wyes.karny@....com>, <gautham.shenoy@....com>, <ananth.narayan@....com>, <linux-pm@...r.kernel.org>, <linux-kernel@...r.kernel.org>, <stable@...r.kernel.org>, Perry Yuan <Perry.Yuan@....com> Subject: [PATCH v2 1/5] cpufreq: amd-pstate: cpufreq: amd-pstate: reset MSR_AMD_PERF_CTL register at init From: Wyes Karny <wyes.karny@....com> MSR_AMD_PERF_CTL is guaranteed to be 0 on a cold boot. However, on a kexec boot, for instance, it may have a non-zero value (if the cpu was in a non-P0 Pstate). In such cases, the cores with non-P0 Pstates at boot will never be pushed to P0, let alone boost frequencies. Kexec is a common workflow for reboot on Linux and this creates a regression in performance. Fix it by explicitly setting the MSR_AMD_PERF_CTL to 0 during amd_pstate driver init. Cc: stable@...r.kernel.org Reviewed-by: Gautham R. Shenoy <gautham.shenoy@....com> Tested-by: Wyes Karny <wyes.karny@....com> Signed-off-by: Wyes Karny <wyes.karny@....com> Signed-off-by: Perry Yuan <Perry.Yuan@....com> --- drivers/cpufreq/amd-pstate.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index ace7d50cf2ac..d844c6f97caf 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -424,12 +424,22 @@ static void amd_pstate_boost_init(struct amd_cpudata *cpudata) amd_pstate_driver.boost_enabled = true; } +static void amd_perf_ctl_reset(unsigned int cpu) +{ + wrmsrl_on_cpu(cpu, MSR_AMD_PERF_CTL, 0); +} + static int amd_pstate_cpu_init(struct cpufreq_policy *policy) { int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret; struct device *dev; struct amd_cpudata *cpudata; + /* + * Resetting PERF_CTL_MSR will put the CPU in P0 frequency, + * which is ideal for initialization process. + */ + amd_perf_ctl_reset(policy->cpu); dev = get_cpu_device(policy->cpu); if (!dev) return -ENODEV; -- 2.25.1
Powered by blists - more mailing lists