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Message-ID: <a9c269cd-5939-7753-9d3e-3bb2e08ccb5b@linaro.org>
Date: Thu, 17 Nov 2022 10:11:41 +0100
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Abel Vesa <abel.vesa@...aro.org>, Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
Mike Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>
Cc: Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
devicetree@...r.kernel.org, linux-arm-msm@...r.kernel.org,
linux-clk@...r.kernel.org
Subject: Re: [PATCH 8/9] dt-bindings: clock: Add SM8550 TCSR CC clock bindings
On 16/11/2022 11:47, Abel Vesa wrote:
> Add bindings documentation for clock TCSR driver on SM8550.
All bindings should go as first patches in the series.
Subject: drop second, redundant "bindings".
>
> Signed-off-by: Abel Vesa <abel.vesa@...aro.org>
> ---
> .../bindings/clock/qcom,tcsrcc-sm8550.yaml | 46 +++++++++++++++++++
> .../dt-bindings/clock/qcom,tcsrcc-sm8550.h | 18 ++++++++
> 2 files changed, 64 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/qcom,tcsrcc-sm8550.yaml
> create mode 100644 include/dt-bindings/clock/qcom,tcsrcc-sm8550.h
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,tcsrcc-sm8550.yaml b/Documentation/devicetree/bindings/clock/qcom,tcsrcc-sm8550.yaml
> new file mode 100644
> index 000000000000..7d7bacb23610
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,tcsrcc-sm8550.yaml
Filename matching compatible.
> @@ -0,0 +1,46 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/qcom,tcsrcc-sm8550.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm TCSR Clock Controller Binding for SM8550
Same issue as your GCC patch.
> +
> +maintainers:
> + - Bjorn Andersson <andersson@...nel.org>
> +
> +description: |
> + Qualcomm TCSR clock control module which supports the clocks,
> + resets and power domains on SM8550
Same issue as your GCC patch.
> +
> + See also:
> + - dt-bindings/clock/qcom,tcsrcc-sm8550.h
Same issue as your GCC patch.
> +
> +properties:
> + compatible:
> + const: qcom,sm8550-tcsrcc
> +
> + '#clock-cells':
> + const: 1
> +
> + '#reset-cells':
> + const: 1
> +
> + reg:
> + maxItems: 1
> +
> +required:
> + - compatible
> +
> +unevaluatedProperties: false
additionalProperties: false instead
> +
> +examples:
> + - |
> + clock-controller@...0000 {
> + compatible = "qcom,sm8550-tcsrcc";
> + reg = <0x1fc0000 0x30000>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> +...
> diff --git a/include/dt-bindings/clock/qcom,tcsrcc-sm8550.h b/include/dt-bindings/clock/qcom,tcsrcc-sm8550.h
> new file mode 100644
> index 000000000000..eda360e84f0a
> --- /dev/null
> +++ b/include/dt-bindings/clock/qcom,tcsrcc-sm8550.h
Filename matching compatible.
> @@ -0,0 +1,18 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
Dual license.
> +/*
> + * Copyright (c) 2022, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2022, Linaro Limited
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_QCOM_TCSR_CC_SM8550_H
> +#define _DT_BINDINGS_CLK_QCOM_TCSR_CC_SM8550_H
> +
> +/* GCC clocks */
> +#define TCSR_PCIE_0_CLKREF_EN 0
> +#define TCSR_PCIE_1_CLKREF_EN 1
> +#define TCSR_UFS_CLKREF_EN 2
> +#define TCSR_UFS_PAD_CLKREF_EN 3
> +#define TCSR_USB2_CLKREF_EN 4
> +#define TCSR_USB3_CLKREF_EN 5
> +
> +#endif
Best regards,
Krzysztof
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